# US 2001/0025366 A1 · Circuit design apparatus, circuit design method, circuit design program, and semiconductor intergrated circuit fabrication method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2001/0025366 A1 - Document ID: US20010025366A1 - Status: Published application - Kind: A1 - Application number: 09/816,244 - Filed: 2001-03-26 - Published: 2001-09-27 - Earliest claimed: 2000-03-27 - Assignees: Kabushiki Kaisha Toshiba - Inventors: Itaru Yamazaki; Nobuyuki Ikumi - Web page: https://patentgrep.com/patent/US20010025366A1 ## CPC - G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In a circuit design method, an arrangement/wiring section (112) determines an arrangement and wiring of logical blocks (40a, 40b, 40c, 40d) so that delay limitation information about input signals supplied to the logical blocks (40a, 40b, 40c, 40d) and limitation conditions about a difference of delay times among a pre-charge control signal (ck0, ck1, ck2) supplied to the corresponding logical block (40a, 40b, 40c, 40d) and the input signals are satisfied. ## Claims ### Claim 1 A circuit design apparatus for determining an arrangement and wiring of logical blocks in a circuit by using circuit design information, comprising an arrangement/wiring section for determining an arrangement and wiring of the logical blocks in the circuit so that both delay limitation information about input signals to be supplied to the logical blocks and limitation conditions about a difference of delay times among a pre-charge control signal to be supplied to the corresponding logical block and the input signals are satisfied. ### Claim 2 (depends on 1) A circuit design apparatus according to claim 1, wherein the delay limitation information for the input signals input by the arrangement/wiring section is limitation information for a delay of each input signal that have been satisfied when the logical blocks are connected, and the limitation conditions about a difference of delay times among a pre-charge control signal to be supplied to the corresponding logical block and the input signals are limitation conditions, each for a difference of delay times caused among the pre-charge control signal supplied to the corresponding logical block and the wirings through which the corresponding input signals are supplied. ### Claim 3 (depends on 1) A circuit design apparatus according to claim 1, wherein the arrangement/wiring section determines the arrangement and the wiring of the logical blocks so that the transmission of the pre-charge control signal is delayed when compared with the transmission delay time of the input signal to be supplied to the logical block by inserting a delay cell that is capable of delaying the transmission delay time of the pre-charge control signal. ### Claim 4 (depends on 2) A circuit design apparatus according to claim 2, wherein the arrangement/wiring section determines the arrangement and the wiring of the logical blocks so that the transmission delay time of the pre-charge control signal is delayed when compared with the transmission delay time of the input signal to be supplied to the logical block by inserting a delay cell that is capable of delaying the transmission delay time of the pre-charge control signal. ### Claim 5 (depends on 1) A circuit design apparatus according to claim 1, further comprising: a delay calculation section for calculating the delay value of the input signal to be supplied to the corresponding logical block by referring to arrangement/wiring information of the logical blocks and a coupling capacity; and a delay improvement section for improving the transmission delay time of the input signal to be supplied to the corresponding logical block by reducing the coupling capacity when the delay value calculated does not satisfy the corresponding limitation condition. ### Claim 6 (depends on 3) A circuit design apparatus according to claim 3, further comprising: a delay calculation section for calculating the delay value of the input signal to be supplied to the corresponding logical block by referring to arrangement/wiring information of the logical blocks and a coupling capacity; and a delay improvement section for improving the transmission delay time of the input signal to be supplied to the corresponding logical block by reducing the coupling capacity when the delay value calculated does not satisfy the corresponding limitation condition. ### Claim 7 A circuit design method of determining an arrangement and wiring of logical blocks in a circuit by using circuit design information, comprising the steps of: inputting delay limitation information about input signals to be supplied to the logical blocks and limitation conditions about a difference of delay times among a pre-charge control signal to be supplied to the corresponding logical block and the input signals; and determining the arrangement and the wiring of the logical blocks in the circuit so that both the delay limitation information and the limitation conditions are satisfied. ### Claim 8 (depends on 7) A circuit design method according to claim 7, wherein in the step of inputting the delay limitation information and the limitation conditions, the delay limitation information for the input signals which are input to the logical blocks are limitation information for a delay of each input signal that have been satisfied when the logical blocks are connected, and the limitation conditions about a difference of delay times among a pre-charge control signal to be supplied to the corresponding logical block and the input signals are limitation conditions, each for a difference of delay times caused among the pre-charge control signal supplied to the corresponding logical block and the wirings through which the corresponding input signals are supplied. ### Claim 9 (depends on 7) A circuit design method according to claim 7, wherein in the step of performing the arrangement and wiring of the logical blocks, the arrangement and the wiring of the logical blocks are determined so that the transmission of the pre-charge control signal is delayed when compared with the transmission delay time of the input signal to be supplied to the logical block by inserting a delay cell that is capable of delaying the transmission delay time of the pre-charge control signal. ### Claim 10 (depends on 8) A circuit design method according to claim 8, wherein in the step of performing the arrangement and wiring of the logical blocks, the arrangement and the wiring of the logical blocks are determined so that the transmission of the pre-charge control signal is delayed when compared with the transmission delay time of the input signal to be supplied to the logical block by inserting a delay cell that is capable of delaying the transmission delay time of the pre-charge control signal. ### Claim 11 (depends on 7) A circuit design method according to claim 7, further comprising the steps of: calculating the delay value of the input signal to be supplied to the corresponding logical block by referring to arrangement/wiring information of the logical blocks and a coupling capacity; and improving the transmission delay time of the input signal to be supplied to the corresponding logical block by reducing the coupling capacity when the delay value calculated does not satisfy the corresponding limitation condition. ### Claim 12 (depends on 9) A circuit design method according to claim 9, further comprising the steps of: calculating the delay value of the input signal to be supplied to the corresponding logical block by referring to arrangement/wiring information of the logical blocks and a coupling capacity; and improving the transmission delay time of the input signal to be supplied to the corresponding logical block by reducing the coupling capacity when the delay value calculated does not satisfy the corresponding limitation condition. ### Claim 13 A circuit design program to be used for executing a circuit design method of determining an arrangement and wiring of logical blocks in a circuit by using circuit design information, comprising the programs of: inputting delay limitation information about input signals to be supplied to the logical blocks and limitation conditions about a difference of delay times among a pre-charge control signal to be supplied to the corresponding logical block and the input signals; and determining the arrangement and the wiring of the logical blocks in the circuit so that both the delay limitation information and the limitation conditions are satisfied. ### Claim 14 (depends on 13) A circuit design program according to claim 13, wherein in the program for inputting the delay limitation information and the limitation conditions, the delay limitation information for the input signals which are input to the logical blocks are limitation information for a delay of each input signal that have been satisfied when the logical blocks are connected, and the limitation conditions about a difference of delay times among a pre-charge control signal to be supplied to the corresponding logical block and the input signals are limitation conditions, each for a difference of delay times caused among the pre-charge control signal supplied to the corresponding logical block and the wirings through which the corresponding input signals are supplied. ### Claim 15 (depends on 13) A circuit design program according to claim 13, wherein in the program for performing the arrangement and wiring of the logical blocks, the arrangement and the wiring of the logical blocks are determined so that the transmission of the pre-charge control signal is delayed when compared with the transmission delay time of the input signal to be supplied to the logical block by inserting a delay cell that is capable of delaying the transmission delay time of the pre-charge control signal. ### Claim 16 (depends on 14) A circuit design program according to claim 14, wherein in the program for performing the arrangement and wiring of the logical blocks, the arrangement and the wiring of the logical blocks are determined so that the transmission of the pre-charge control signal is delayed when compared with the transmission delay time of the input signal to be supplied to the logical block by inserting a delay cell that is capable of delaying the transmission delay time of the pre-charge control signal. ### Claim 17 (depends on 13) A circuit design program according to claim 13, further comprising the programs of: calculating the delay value of the input signal to be supplied to the corresponding logical block by referring to arrangement/wiring information of the logical blocks and a coupling capacity; and improving the transmission delay time of the input signal to be supplied to the corresponding logical block by reducing the coupling capacity when the delay value calculated does not satisfy the corresponding limitation condition. ### Claim 18 (depends on 15) A circuit design program according to claim 15, further comprising the programs of: calculating the delay value of the input signal to be supplied to the corresponding logical block by referring to arrangement/wiring information of the logical blocks and a coupling capacity; and improving the transmission delay time of the input signal to be supplied to the corresponding logical block by reducing the coupling capacity when the delay value calculated does not satisfy the corresponding limitation condition. ### Claim 19 A semiconductor integrated circuit fabrication method of fabricating a semiconductor integrated circuit, comprising the steps of: inputting circuit design information obtained by determining an arrangement and wiring of logical blocks so that the following delay limitation information and limitation conditions are satisfied: the delay limitation information about input signals to be supplied to the logical blocks; and the limitation conditions about a difference of delay times among a pre-charge control signal to be supplied to the corresponding logical block and the input signals; and fabricating the semiconductor integrated circuit by performing the arrangement and wiring of the logical blocks based on the circuit design information.