# US 2001/0023992 A1 · Highly integrated system-on-chip system with non-volatile memory unit

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- Number: US 2001/0023992 A1
- Document ID: US20010023992A1
- Status: Published application
- Kind: A1
- Application number: 09/817,964
- Filed: 2001-03-27
- Published: 2001-09-27
- Earliest claimed: 2000-03-27
- Inventors: Andreas Doll
- Web page: https://patentgrep.com/patent/US20010023992A1

## CPC

- H10W 90/00: Package configurations
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- G11C 11/15: using multiple magnetic layers (G11C11/155 takes precedence)
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A highly integrated system-on-chip system with a non-volatile memory unit, includes a chip having an integrated MRAM memory unit, and semiconductor layers disposed underneath the MRAM memory unit and functioning merely as carriers for the MRAM memory unit. An integration density of the chip may be increased by using the semiconductor layers for additional integrated circuits.

## Claims

### Claim 1

A chip, comprising:
a semiconductor substrate; and
an integrated circuit disposed above said semiconductor substrate;
said integrated circuit containing an MRAM (Magnetoresistive Random Access Memory) memory unit having a memory cell field; and
said integrated circuit containing parts implemented in said semiconductor substrate underneath said memory unit, and said parts containing additional memory units.

### Claim 2 (depends on 1)

The chip according to claim 1, wherein said parts of said integrated circuit implemented underneath said memory unit also contain a drive logic for said MRAM memory cell field.

### Claim 3 (depends on 1)

The chip according to claim 1, wherein said additional memory units are SRAM (Synchronous Random Access Memory) based memory cell fields.

### Claim 4 (depends on 1)

The chip according to claim 1, wherein said additional memory units are DRAM (Dynamic Random Access Memory) based memory cell fields.

### Claim 5 (depends on 1)

The chip according to claim 1, wherein said semiconductor substrate has an upper part with at least one semiconductor layer.

### Claim 6 (depends on 5)

The chip according to claim 5, wherein said parts of said integrated circuit implemented underneath said memory unit are disposed in said at least one semiconductor layer.

### Claim 7 (depends on 1)

The chip according to claim 1, wherein said semiconductor substrate has a lower part constructed of a material largely formed of silicon.