# US 2001/0023980 A1 · Stacked semiconductor device and semiconductor system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2001/0023980 A1 - Document ID: US20010023980A1 - Status: Published application - Kind: A1 - Application number: 09/739,256 - Filed: 2000-12-19 - Published: 2001-09-27 - Earliest claimed: 1999-12-20 - Assignees: Kabushiki Kaisha Toshiba - Inventors: Jun Ohmori - Web page: https://patentgrep.com/patent/US20010023980A1 ## CPC - H10W 72/0198: {batch processes} - H10W 90/00: Package configurations - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/801: {Interconnections on sidewalls of containers} - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/722: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A stacked semiconductor device includes a plurality of stacked wiring substrates each having connection electrodes and wires connected to the connection electrodes and each mounted with a semiconductor device, a plurality of conductive via boards each interposed between adjacent two wiring substrates and having an opening for enclosing the semiconductor device, an uppermost wiring substrate formed on the top of the stacked wiring substrates and having wires connected to the connection electrodes, and a lowermost wiring substrate formed under the stacked wiring substrates and having wires connected to the connection electrodes, wherein heat radiation/shield conductive layers are formed on the uppermost and lowermost wiring substrates. ## Claims ### Claim 1 A stacked semiconductor device comprising: a plurality of stacked wiring substrates each including a plurality of via-holes in which connection electrodes are formed and wires electrically connected to the connection electrodes; an uppermost wiring substrate stacked on a top of the stacked wiring substrates and including a plurality of via-holes in which connection electrodes are formed and wires electrically connected to the connection electrodes; a plurality of semiconductor devices mounted on the respective wiring substrates and electrically connected to the wires thereof; a plurality of conductive via insulation substrates each having a cavity which is larger than the semiconductor device enclosed therein and each including a plurality of via-holes in which connection electrodes are formed, each of the conductive via insulation substrates being stacked on each of the wiring substrates; and a plurality of conductive layers formed on a top surface of the uppermost wiring substrate and/or a bottom surface of a lowermost wiring substrate formed under the stacked wiring substrates, wherein the wiring substrates, the uppermost wiring substrate, and the conductive via insulation substrates are electrically connected to each other by the connection electrodes. ### Claim 2 (depends on 1) The stacked semiconductor device according to claim 1, wherein the conductive layers are used as external connection terminals. ### Claim 3 (depends on 2) The stacked semiconductor device according to claim 2, wherein the external connection terminals each has a diameter of 1 mm or more and an area of 1 mm2 or larger. ### Claim 4 (depends on 1) The stacked semiconductor device according to claim 1, wherein at least one of the connection electrodes of the wiring substrates, the uppermost wiring substrate, and the conductive via insulation substrates is connected to a ground line, and at least one of the conductive layers is electrically connected to the ground line through the connection electrodes. ### Claim 5 (depends on 2) The stacked semiconductor device according to claim 2, wherein at least one of the connection electrodes of the wiring substrates, the uppermost wiring substrate, and the conductive via insulation substrates is connected to a ground line, and at least one of the conductive layers is electrically connected to the ground line through the connection electrodes. ### Claim 6 (depends on 3) The stacked semiconductor device according to claim 3, wherein at least one of the connection electrodes of the wiring substrates, the uppermost wiring substrate, and the conductive via insulation substrates is connected to a ground line, and at least one of the conductive layers is electrically connected to the ground line through the connection electrodes. ### Claim 7 (depends on 1) The stacked semiconductor device according to claim 1, wherein at least one of the conductive layers serves as a heat radiation layer. ### Claim 8 (depends on 2) The stacked semiconductor device according to claim 2, wherein at least one of the conductive layers serves as a heat radiation layer. ### Claim 9 (depends on 3) The stacked semiconductor device according to claim 3, wherein at least one of the conductive layers serves as a heat radiation layer. ### Claim 10 (depends on 4) The stacked semiconductor device according to claim 4, wherein at least one of the conductive layers serves as a heat radiation layer. ### Claim 11 (depends on 1) The stacked semiconductor device according to claim 1, wherein an area of the conductive layers occupying one surface of the uppermost wiring substrate and the lowermost wiring substrate ranges from 50% to 95%. ### Claim 12 (depends on 2) The stacked semiconductor device according to claim 2, wherein an area of the conductive layers occupying one surface of the uppermost wiring substrate and the lowermost wiring substrate ranges from 50% to 95%. ### Claim 13 (depends on 3) The stacked semiconductor device according to claim 3, wherein an area of the conductive layers occupying one surface of the uppermost wiring substrate and the lowermost wiring substrate ranges from 50% to 95%. ### Claim 14 (depends on 4) The stacked semiconductor device according to claim 4, wherein an area of the conductive layers occupying one surface of the uppermost wiring substrate and the lowermost wiring substrate ranges from 50% to 95%. ### Claim 15 (depends on 1) The stacked semiconductor device according to claim 1, wherein the connection electrodes formed in the via-holes of the wiring substrates, the uppermost wiring substrate, and the conductive via insulation substrates are exposed to side walls of the stacked semiconductor device. ### Claim 16 (depends on 4) The stacked semiconductor device according to claim 4, wherein the connection electrodes formed in the via-holes of the wiring substrates, the uppermost wiring substrate, and the conductive via insulation substrates are exposed to side walls of the stacked semiconductor device. ### Claim 17 (depends on 15) The stacked semiconductor device according to claim 15, wherein the connection electrodes exposed to the side walls of the stacked semiconductor device serve as external connection terminals. ### Claim 18 (depends on 1) The stacked semiconductor device according to claim 1, wherein each of the semiconductor device has a thickness of 30 μm to 200 μm. ### Claim 19 (depends on 4) The stacked semiconductor device according to claim 4, wherein each of the semiconductor device has a thickness of 30 μm to 200 μm. ### Claim 20 A stacked semiconductor system comprising a module substrate having spring terminals which hold a stacked semiconductor device having external connection terminals, wherein the external connection terminals are pressed by the spring terminals. ### Claim 21 (depends on 20) A stacked semiconductor system according to claim 20, wherein at least one of the spring terminals is connected to a ground line.