# US 2001/0023960 A1 · Method for manufacturing semiconductor device and insulated gate type power transistor

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- Number: US 2001/0023960 A1
- Document ID: US20010023960A1
- Status: Published application
- Kind: A1
- Application number: 09/790,888
- Filed: 2001-02-23
- Published: 2001-09-27
- Earliest claimed: 2000-02-28
- Assignees: Denso Corporation
- Inventors: Hajime Soga; Kenji Kondo; Eiji Ishikawa; Yoshikazu Sakano; Mikimasa Suzuki
- Web page: https://patentgrep.com/patent/US20010023960A1

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 10/041: {of isolation regions comprising polycrystalline semiconductor materials}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/40: Isolation regions comprising polycrystalline semiconductor materials
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In a method for manufacturing a semiconductor device, first, a trench is formed on a semiconductor substrate by anisotropic etching, and a reaction product is produced and deposited on the inner wall of the trench during the anisotropic etching. Then, isotropic etching is performed to round a corner of a bottom portion of the trench without removing the reaction product. The isotropic etching can round the corner of the trench without etching the side wall of the trench that is covered by the reaction product.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, comprising:
performing anisotropic etching to form a trench on a semiconductor substrate, the anisotropic etching being accompanied by deposition of a reaction product on an inner wall of the trench; and
performing isotropic etching to round a corner of a bottom portion of the trench using the reaction product as a mask.

### Claim 2 (depends on 1)

The method of claim 1, wherein the anisotropic etching is performed in an etching apparatus in which the isotropic etching are performed successively.

### Claim 3 (depends on 1)

The method of claim 1, wherein the isotropic etching is dry etching that is performed using a gas containing fluorine.

### Claim 4 (depends on 3)

The method of claim 3, wherein the isotropic etching is performed under an etching condition, which suppresses etching by ions in a thickness direction perpendicular to a surface of the semiconductor substrate, and enhances etching by radicals in a lateral direction parallel to the surface of the semiconductor substrate.

### Claim 5 (depends on 1)

The method of claim 1, wherein the isotropic etching is wet etching.

### Claim 6 (depends on 1)

The method of claim 1, wherein the trench is formed by the anisotropic etching to have a side wall that is tapered from a surface of the semiconductor substrate in a depth direction.

### Claim 7 (depends on 6)

The method of claim 6, wherein the anisotropic etching is performed under an etching condition so that a maximum width of the bottom portion of the trench is approximately smaller than a width of an upper portion of the trench after the isotropic etching is etched.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
removing the reaction product from the inner wall of the trench after the isotropic etching is performed to round the corner as first isotropic etching; and
performing second isotropic etching after the reaction product is removed.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
removing the reaction product from the inner wall of the trench after the isotropic etching is performed to round the corner as first isotropic etching; and
performing annealing for removing damages after the reaction product is removed.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
removing the reaction product from the inner wall of the trench after the isotropic etching is performed to round the corner as first isotropic etching;
performing sacrificial oxidation after the reaction product is removed.

### Claim 11 (depends on 1)

The method of claim 1, wherein:
the anisotropic etching is performed using a first gas containing bromine, fluorine and oxygen; and
the isotropic etching is performed using a second gas different from the first gas.

### Claim 12 (depends on 11)

The method of claim 11, wherein the second gas contains fluorine.

### Claim 13 (depends on 1)

The method of claim 1, wherein the corner is rounded to have a radius of curvature in a range of about 0.3 μm to 0.5 μm.

### Claim 14 (depends on 1)

The method of claim 1, wherein:
the reaction product produced by the anisotropic etching is made of an oxide based material and deposited on the inner wall of the trench;
a thickness of the reaction product at the bottom portion of the trench is thinner than that at the inner wall other than the bottom portion; and
the isotropic etching is performed to round the corner through the reaction product.

### Claim 15 (depends on 1)

The method of claim 1, wherein:
the bottom portion of the trench expands in a lateral direction by the isotropic etching to thereby form a laterally expanding portion of the trench.

### Claim 16 (depends on 15)

The method of claim 15, wherein:
the trench is formed by the anisotropic etching to taper from a surface of the semiconductor substrate in a depth direction; and
the expanding portion is formed by the isotropic etching to have the width that is approximately smaller than that of an opening portion of the trench.

### Claim 17

An insulated gate type power transistor, comprising:
a semiconductor substrate having a trench formed thereon by anisotropic etching, the trench having a corner of a bottom portion that is rounded by isotropic etching using, as a mask, a reaction product that is produced by the anisotropic etching; and
a gate electrode disposed in the trench and having a lower end portion that is rounded.

### Claim 18 (depends on 17)

The insulated gate type power transistor of claim 17, wherein the corner of the bottom portion of the trench has a radius of curvature in a range of about 0.3 μm to 0.5 μm.

### Claim 19 (depends on 17)

The insulated gate type power transistor of claim 17, wherein:
the trench tapers from an opening portion thereof toward the bottom portion; and
the bottom portion of the trench expands in a direction parallel to a surface of the semiconductor substrate.

### Claim 20 (depends on 19)

The insulated gate type power transistor of claim 19, wherein a width of the bottom portion of the trench is approximately smaller than a width of the opening portion.

### Claim 21

An insulated gate type power transistor comprising:
a semiconductor substrate composed of a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type disposed on the first semiconductor region, and a third semiconductor region of the first conductivity type disposed on the second semiconductor region and forming a main surface of the semiconductor substrate; and
a gate electrode disposed in a trench via a gate insulating film, thereby forming a MOS structure in which a channel region is provided on a surface of the second semiconductor region opposed to the gate electrode on a side wall of the trench with the gate insulating film interposed therebetween, wherein:
the trench has a straight portion extending in the second and third semiconductor regions from the main surface in a vertical direction vertical to the main surface so as to reach the first semiconductor region, and an expanding portion expanding from a bottom end of the straight portion in a lateral direction parallel to the main surface and forming a bottom portion of the trench, an entirety of the expanding portion being contained in the first semiconductor region.

### Claim 22 (depends on 21)

The insulated gate type power transistor of claim 21, wherein the straight portion is tapered to prevent a maximum width of the expanding portion in the lateral direction from exceeding an opening width of the trench opening on the main surface.

### Claim 23 (depends on 1)

The insulated gate type power transistor of claim 1, further comprising a fourth semiconductor region underlying the first semiconductor region at an opposite side with respect to the second semiconductor region, the fourth semiconductor region having an impurity concentration higher than that of the first semiconductor region.