# US 2001/0023950 A1 · Ferrpelectric memory device having a ferroelectric capacitor disposed on an extended active area

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- Number: US 2001/0023950 A1
- Document ID: US20010023950A1
- Status: Published application
- Kind: A1
- Application number: 09/740,946
- Filed: 2000-12-21
- Published: 2001-09-27
- Earliest claimed: 1999-12-28
- Assignees: Hyundai Electronics Industries Co., Ltd.
- Inventors: Jae-Whan Kim
- Web page: https://patentgrep.com/patent/US20010023950A1

## CPC

- G11C 11/22: using ferroelectric elements
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Disclosed is a ferroelectric memory device, which prevents a potential difference across a ferroelectric capacitor from being occurred and minimizes a step to be induced during the fabrication of the capacitor. The memory device comprises a first switching transistor having its gate coupled to a positive wordline, and its source and drain coupled between a bitline and a first node respectively; a ferroelectric capacitor coupled between the first node and a plateline; and a second switching transistor having its gate coupled to a negative wordline, and its source and drain coupled to the first node and the plateline respectively. A second node at which the source of the second switching transistor and the plateline are contacted is formed on an active area locating between two adjacent negative wordlines; and the ferroelectric capacitor is formed on the active area. The active area is broadly formed to prevent a resistance of the second node from being occurred.

## Claims

### Claim 1

A ferroelectric memory device, comprising:
a first switching transistor having a gate coupled to a positive wordline, and a source and a drain coupled between a bitline and a first node;
a ferroelectric capacitor in an active area between a pair of adjacent negative wordlines and coupled between the first node and a plateline; and
a second switching transistor having a gate coupled to a negative wordline, and a source and a drain coupled to the first node and the plateline, respectively, the source of the second switching transistor and the plateline contacting a second node in the active area.

### Claim 2 (depends on 1)

The ferroelectric memory device of claim 1, wherein the active area is sufficiently large to incur no resistance in the second node.

### Claim 3 (depends on 1)

The ferroelectric memory device of claim 1, wherein the positive and negative wordlines are in parallel with one another and pass through a field oxidation area, and a pair of adjacent positive wordlines are surrounded by a pair of the negative wordlines; and
wherein the bitline electrically contracts the active area, which is surrounded by a pair of the positive wordlines and a pair of the field oxidation areas, and passes through the field oxidation area.

### Claim 4 (depends on 3)

The ferroelectric memory device of claim 3, wherein the ferroelectric capacitor electrically contact the active area which is positioned at a portion surrounded by the positive wordline, the negative wordline and the two field oxidation areas, through a connection wire.