# US 2001/0022752 A1 · Method and apparatus for rapidly testing memory devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2001/0022752 A1 - Document ID: US20010022752A1 - Status: Published application - Kind: A1 - Application number: 09/754,005 - Filed: 2001-01-02 - Published: 2001-09-20 - Earliest claimed: 1997-02-28 - Assignees: Micron Technology, Inc. - Inventors: Kevin G. Duesman - Web page: https://patentgrep.com/patent/US20010022752A1 ## CPC - G11C 29/34: Accessing multiple bits simultaneously - G11C 29/36: Data generation devices, e.g. data inverters - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A circuit transfers data in an array of memory cells arranged in rows and columns. The circuit includes a plurality of row lines, a plurality of pairs of complementary digit lines, and an array of memory cells, each memory cell having a control terminal coupled to one of the row lines and a data terminal coupled to one of the complementary digit lines of one of the pairs of complementary digit lines responsive to a row enable signal on the row line of the row corresponding to the memory cell. A plurality of sense amplifiers are included in the circuit, each sense amplifier coupled to an associated pair of first and second complementary digit lines which senses a voltage differential between the first and second complementary digit lines and, in response to the sensed voltage differential, drives the first and second complementary digit lines to voltage levels corresponding to complementary logic states. A plurality of equilibration circuits are also included in the circuit, each equilibration circuit coupled between one of the pairs of complementary digit lines and operable to equalize the voltage level on each pair of complementary digit lines to a predetermined level responsive to an equilibration signal. A control circuit is coupled to the plurality of row lines and the equilibration circuits. The control circuit is operable to: write a pattern of data to an initial row of the memory array; generate the equilibrate signal; apply a row enable signal to the row line of the memory cells in the initial row; terminate the row enable signal for the initial row; apply a row enable signal to the row line to which the memory cells in another row are connected; terminate the row enable signal for the another row; and generate the equilibrate signal. ## Claims ### Claim 1 A circuit for transferring data in an array of memory cells arranged in rows and columns, comprising: a plurality of row lines; a plurality of pairs of complementary digit lines; an array of memory cells, each memory cell having a control terminal coupled to one of the row lines and a data terminal coupled to one of the complementary digit lines of one of the pairs of complementary digit lines responsive to a row enable signal on the row line of the row corresponding to the memory cell; a plurality of sense amplifiers, each sense amplifier coupled to an associated pair of first and second complementary digit lines which senses a voltage differential between the first and second complementary digit lines and, in response to the sensed voltage differential, drives the first and second complementary digit lines to voltage levels corresponding to complementary logic states; a plurality of equilibration circuits, each equilibration circuit coupled between one of the pairs of complementary digit lines operable to equalize the voltage level on each pair of complementary digit lines to a predetermined level responsive to an equilibrate signal; and a control circuit coupled to the plurality of row lines, and the equilibration circuits, the control circuit operable to: write a pattern of data to an initial row of the memory array; generate the equilibrate signal; apply a row enable signal to the row line of the memory cells in the initial row; terminate the row enable signal for the initial row; apply a row enable signal to the row line to which the memory cells in another row are connected; terminate the row enable signal for the another row; and generate the equilibrate signal. ### Claim 2 (depends on 1) The circuit of claim 1 wherein each sense amplifier comprises: a first sense switch having a control terminal coupled to the second complementary digit line, a first signal terminal coupled to a common reference voltage level, and a second signal terminal coupled to the first complementary digit line; a second sense switch having a control terminal coupled to the first complementary digit line, a first signal terminal coupled to the common reference voltage level, and a second signal terminal coupled to the second complementary digit line; a third sense switch having a control terminal coupled to the second complementary digit line, a first signal terminal coupled to a supply voltage Vcc, and a second signal terminal coupled to the first complementary digit line; and a fourth sense switch having a control terminal coupled to the first complementary digit line, a first signal terminal coupled to the supply voltage Vcc, and a second signal terminal coupled to the second complementary digit line. ### Claim 3 (depends on 2) The circuit of claim 2 wherein the first and second sense switches are NMOS transistors, and the third and fourth sense switches are PMOS transistors. ### Claim 4 (depends on 1) The circuit of claim 1 wherein each equilibration circuit comprises: a first equilibration switch having a control terminal, a first signal terminal coupled to the first complementary digit line and a second signal terminal coupled to the second complementary digit line; a second equilibration switch having a control terminal coupled to the control terminal of the first equilibration switch, a first signal terminal coupled to the first complementary digit line and a second signal terminal coupled to a reference voltage source; and a third equilibration switch having a control terminal coupled to the control terminal of the first equilibration switch, a first signal terminal coupled to the second complementary digit line and a second signal terminal coupled to the reference voltage source. ### Claim 5 (depends on 4) The circuit of claim 4 wherein each of the equilibration switches is a transistor and wherein the reference voltage source provides a voltage level of approximately Vcc/2. ### Claim 6 (depends on 1) The circuit of claim 1 wherein each memory cell comprises: a storage element having a first storage terminal and a second storage terminal, the second storage terminal coupled to a reference voltage source of approximately Vcc/2; and a memory switch circuit having a control terminal coupled to an associated row line, a first data terminal coupled to the first storage terminal of the storage element, and a second data terminal coupled to one of the associated first and second complementary digit lines. ### Claim 7 A circuit for testing an array of memory cells arranged in rows and columns, comprising: a plurality of row lines; a plurality of pairs of complementary digit lines; an array of memory cells, each memory cell having a control terminal coupled to one of the row lines and a data terminal coupled to one of the complementary digit lines of one of the pairs of complementary digit lines responsive to a row enable signal on the row line of the row corresponding to the memory cell; a plurality of sense amplifiers, each sense amplifier coupled to an associated pair of first and second complementary digit lines which senses a voltage differential between the first and second complementary digit lines and, in response to the sensed voltage differential, drives the first and second complementary digit lines to voltage levels corresponding to complementary logic states; a plurality of equilibration circuits, each equilibration circuit coupled between one of the pairs of complementary digit lines operable to equalize the voltage level on each pair of complementary digit lines to a predetermined level responsive to an equilibrate signal; and a control circuit coupled to the plurality of row lines, and the equilibration circuits, the control circuit operable to: write a pattern of data to an initial row of memory cells in the memory array; generate the equilibrate signal; apply a row enable signal to the row line of the memory cells in the initial row; terminate the row enable signal for the initial row; apply a row enable signal to the row line of the memory cells in a subsequent row; terminate the row enable signal for the subsequent row; generate the equilibrate signal; read the data stored in the subsequent row of the memory array; and\ compare the data read from the subsequent row of memory cells to the data written to the initial row to detect a defective memory cell. ### Claim 8 (depends on 7) The circuit of claim 7 wherein each sense amplifier comprises: a first sense switch having a control terminal coupled to the second complementary digit line, a first signal terminal coupled to a common reference voltage level, and a second signal terminal coupled to the first complementary digit line; a second sense switch having a control terminal coupled to the first complementary digit line, a first signal terminal coupled to the common reference voltage level, and a second signal terminal coupled to the second complementary digit line; a third sense switch having a control terminal coupled to the second complementary digit line, a first signal terminal coupled to a supply voltage Vcc, and a second signal terminal coupled to the first complementary digit line; and a fourth sense switch having a control terminal coupled to the first complementary digit line, a first signal terminal coupled to the supply voltage Vcc, and a second signal terminal coupled to the second complementary digit line. ### Claim 9 (depends on 8) The circuit of claim 8 wherein the first and second sense switches are NMOS transistors, and the third and fourth sense switches are PMOS transistors. ### Claim 10 (depends on 7) The circuit of claim 7 wherein each equilibration circuit comprises: a first equilibration switch having a control terminal, a first signal terminal coupled to the first complementary digit line and a second signal terminal coupled to the second complementary digit line; a second equilibration switch having a control terminal coupled to the control terminal of the first equilibration switch, a first signal terminal coupled to the first complementary digit line and a second signal terminal coupled to a reference voltage source; and a third equilibration switch having a control terminal coupled to the control terminal of the first equilibration switch, a first signal terminal coupled to the second complementary digit line and a second signal terminal coupled to the reference voltage source. ### Claim 11 (depends on 10) The circuit of claim 10 wherein each of the equilibration switches is a transistor and wherein the reference voltage source provides a voltage level of approximately Vcc/2. ### Claim 12 (depends on 7) The circuit of claim 7 wherein each memory cell comprises: a storage element having a first storage terminal and a second storage terminal, the second storage terminal coupled to a reference voltage source of approximately Vcc/2; and a memory switch circuit having a control terminal coupled to an associated row line, a first data terminal coupled to the first storage terminal of the storage element, and a second data terminal coupled to one of the associated first and second complementary digit lines. ### Claim 13 A dynamic random access memory device, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a control circuit coupled the control bus; a read/write circuit coupled to the data bus; and a memory-cell array coupled to the address decoder, control circuit, and read/write circuit, including a plurality of row lines; a plurality of pairs of complementary digit lines; an array of memory cells, each memory cell having a control terminal coupled to one of the row lines and a data terminal coupled to one of the complementary digit lines of one of the pairs of complementary digit lines responsive to a row enable signal on the row line of the row corresponding to the memory cell; a plurality of sense amplifiers, each sense amplifier coupled to an associated pair of first and second complementary digit lines which senses a voltage differential between the first and second complementary digit lines and, in response to the sensed voltage differential, drives the first and second complementary digit lines to voltage levels corresponding to complementary logic states; a plurality of equilibration circuits, each equilibration circuit coupled between one of the pairs of complementary digit lines operable to equalize the voltage level on each pair of complementary digit lines to a predetermined level responsive to an equilibrate signal; and a control circuit coupled to the plurality of row lines, and the equilibration circuits, the control circuit operable to: write a pattern of data to an initial row of the memory array; generate the equilibrate signal; apply a row enable signal to the row line of the memory cells in the initial row; terminate the row enable signal for the initial row; apply a row enable signal to the row line to which the memory cells in another row are connected; terminate the row enable signal for the another row; and generate the equilibrate signal. ### Claim 14 (depends on 13) The device of claim 13 wherein each memory cell comprises: a storage element having a first storage terminal and a second storage terminal, the second storage terminal coupled to a reference voltage source of approximately Vcc/2; and a memory switch circuit having a control terminal coupled to an associated row line, a first data terminal coupled to the first storage terminal of the storage element, and a second data terminal coupled to one of the associated first and second complementary digit lines. ### Claim 15 A computer system, comprising: a data input device; a data output device; an address bus; a data bus; a control bus; and computing circuitry coupled to the data input and output devices, and the data, address, and control busses, the computing circuitry including a memory device that includes, a plurality of row lines; a plurality of pairs of complementary digit lines; an array of memory cells, each memory cell having a control terminal coupled to one of the row lines and a data terminal coupled to one of the complementary digit lines of one of the pairs of complementary digit lines responsive to a row enable signal on the row line of the row corresponding to the memory cell; a plurality of sense amplifiers, each sense amplifier coupled to an associated pair of first and second complementary digit lines which senses a voltage differential between the first and second complementary digit lines and, in response to the sensed voltage differential, drives the first and second complementary digit lines to voltage levels corresponding to complementary logic states; a plurality of equilibration circuits, each equilibration circuit coupled between one of the pairs of complementary digit lines operable to equalize the voltage level on each pair of complementary digit lines to a predetermined level responsive to an equilibrate signal; and a control circuit coupled to the plurality of row lines, and the equilibration circuits, the control circuit operable to: write a pattern of data to an initial row of the memory array; generate the equilibrate signal; apply a row enable signal to the row line of the memory cells in the initial row; terminate the row enable signal for the initial row; apply a row enable signal to the row line to which the memory cells in another row are connected; terminate the row enable signal for the another row; and generate the equilibrate signal. ### Claim 16 A method for transferring data in a memory-cell array arranged in rows and columns, comprising the steps of: writing a test pattern of data into an initial row of memory cells; equilibrating the memory-cell array; activating the initial row of memory cells thereby transferring data stored in the initial row of memory cells to respective sense amplifiers; activating a subsequent row of memory cells so the data stored in the sense amplifiers is copied into the memory cells in the subsequent row of memory cells; and repeating the steps of equilibrating the memory-cell array, activating the initial row and activating a subsequent row until data has been stored in a plurality of rows. ### Claim 17 (depends on 16) The method of claim 16 wherein the step of writing a test pattern of data includes the step of writing a test pattern of data into the first row of memory cells in the memory cell array. ### Claim 18 (depends on 17) The method of claim 17 wherein the step of repeating is performed until data has been stored in all the memory cells in the memory cell array. ### Claim 19 (depends on 16) The method of claim 16 wherein the step of writing a test pattern of data writes an alternating bit pattern of data to the initial row of memory cells. ### Claim 20 (depends on 19) The method of claim 19 wherein the alternating bit pattern comprises 1010 . . . with the first binary 1 being written to the memory cell in the first column of the initial row. ### Claim 21 (depends on 19) The method of claim 19 wherein the alternating bit pattern comprises 0101 . . . with the first binary 0 being written to the memory cell in the first column of the initial row. ### Claim 22 A method for testing memory cells in a memory-cell array arranged in rows and columns, comprising the steps of: writing a test pattern of data into an initial row of memory cells; equilibrating the memory-cell array; activating the initial row of memory cells thereby transferring data stored in the initial row of memory cells to respective sense amplifiers; activating a subsequent row of memory cells so the data stored in the sense amplifiers is copied into the memory cells in the subsequent row of memory cells; repeating the steps of equilibrating the memory-cell array, activating the initial row and activating a subsequent row until data has been stored in a plurality of rows; reading the data that has been stored in one of the rows of memory cells; and comparing the data read from one of the rows of memory cells with the data written to the initial row of memory cells to detect a defective memory cell. ### Claim 23 (depends on 22) The method of claim 22 wherein the step of writing a test pattern of data includes the step of writing a test pattern of data into the first row of memory cells in the memory cell array; ### Claim 24 (depends on 23) The method of claim 23 wherein the step of repeating is performed until data has been stored in all the memory cells in the memory cell array; ### Claim 25 (depends on 24) The method of claim 24 wherein the step of reading the data includes the step of reading the data that has been stored in the last row of memory cells in the memory cell array; ### Claim 26 (depends on 25) The method of claim 25 wherein the step of comparing the data read includes the step of comparing the data read from the last row of memory cells with the data written to the first row of memory cells to detect a defective memory cell. ### Claim 27 (depends on 22) The method of claim 22, further including a step which is executed when the step of comparing the data read detects a defective memory cell in the memory-cell array, the step comprising performing a binary search on the memory-cell array to identify the row containing the defective memory cell. ### Claim 28 (depends on 22) The method of claim 22 wherein the step of writing a test pattern of data includes the step of writing an alternating bit pattern of data to the initial row of memory cells. ### Claim 29 (depends on 28) The method of claim 28 wherein the alternating bit pattern comprises 1010 . . . with the first binary 1 being written to the memory cell in the first column of the initial row. ### Claim 30 (depends on 28) The method of claim 28 wherein the alternating bit pattern comprises 0101 . . . with the first binary 0 being written to the memory cell in the first column of the initial row. ### Claim 31 A method for testing memory cells in a memory-cell array arranged in rows and columns, Comprising the steps of: writing a test pattern of data into a first even row of memory cells; writing a test pattern of data into a first odd row of memory cells; equilibrating the memory-cell array; activating the first even row of memory cells thereby transferring data stored in the first even row of memory cells to respective sense amplifiers; activating a subsequent even row of memory cells so the data stored in the sense amplifiers is copied into the memory cells in the subsequent even row of memory cells; equilibrating the memory-cell array; activating the first odd row of memory cells thereby transferring data stored in the first odd row of memory cells to respective sense amplifiers; activating a subsequent odd row of memory cells so the data stored in the sense amplifiers is copied into the memory cells in the subsequent odd row of memory cells; repeating the steps of equilibrating, activating the first even row, activating a subsequent even row, equilibrating, activating the first odd row and activating a subsequent odd row on successive even and odd rows until data has been stored in the last even and odd rows of the memory-cell array; reading data from the last even and odd rows of the memory-cell array; and comparing data read from the last even and odd rows against the data written to the first even and odd rows, respectively, to detect a defective memory cell in the memory-cell array. ### Claim 32 (depends on 31) The method of claim 31 wherein the steps of writing a test pattern of data into the first even and odd rows include the step of writing alternating bit patterns of data to the first even and odd rows, respectively. ### Claim 33 (depends on 32) The method of claim 32 wherein the alternating bit pattern written to the first even row comprises 1010 . . . with the first binary 1 being written to the memory cell in the first column of the first even row. ### Claim 34 (depends on 33) The method of claim 33 wherein the alternating bit pattern written to the first odd row comprises 0101 . . . with the first binary 0 being written to the memory cell in the first column of the first odd row.