# US 2001/0022751 A1 · Redundancy circuit of semiconductor memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2001/0022751 A1 - Document ID: US20010022751A1 - Status: Published application - Kind: A1 - Application number: 09/861,843 - Filed: 2001-05-22 - Published: 2001-09-20 - Earliest claimed: 1999-03-18 - Assignees: Kabushiki Kaisha Toshiba - Inventors: Takeshi Nagai - Web page: https://patentgrep.com/patent/US20010022751A1 ## CPC - G11C 29/808: {using a flexible replacement scheme} - G11C 29/812: {using a reduced amount of fuses} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor has eight banks that can be accessed simultaneously. Within each bank, there are disposed two fixed spare row decoders and two mapping spare row decoders. Within each bank, two fixed fuse sets are provided corresponding to the fixed spare row decoders. Eight mapping fuse sets are provided at the outside of each bank, for example, with no association with the mapping spare row decoders. Each mapping fuse set stores mapping data for determining a correspondence of the mapping fuse set to a specific mapping spare row decoder within a specific bank. ## Claims ### Claim 1 A semiconductor memory comprising: a normal decoder; a fixed spare decoder for relieving the normal decoder; a fixed memory disposed in association with the fixed spare decoder; a mapping spare decoder for relieving the normal decoder; and a mapping memory disposed independent of the mapping spare decoder, and for being recorded with mapping data, wherein the normal decoder is replaced with the fixed spare decoder when a fail address for selecting the normal decoder is registered in the fixed memory, and the normal decoder is replaced with the mapping spare decoder when the fail address is registered in the mapping memory and also when the mapping data selects the mapping spare decoder. ### Claim 2 (depends on 1) A semiconductor memory according to claim 1, wherein the fixed spare decoder and the mapping spare decoder are connected to one spare word line respectively, when the normal decoder is connected to one word line. ### Claim 3 (depends on 1) A semiconductor memory according to claim 1, wherein the fixed spare decoder and the mapping spare decoder are connected to n (n is a plural number) spare word lines respectively, when the normal decoder is connected to n word lines. ### Claim 4 (depends on 1) A semiconductor memory according to claim 1, wherein the fixed memory and the mapping memory are structured by nonvolatile memories respectively. ### Claim 5 A semiconductor memory comprising: a plurality of banks, each bank having a normal decoder, a fixed spare decoder for relieving the normal decoder, a fixed memory disposed in association with the fixed spare decoder, and a mapping spare decoder for relieving the normal decoder; and a mapping memory disposed at the outside of the plurality of banks, and for being registered with mapping data, wherein the mapping data has a function of associating the mapping memory with the mapping spare decoder within one of the plurality of banks, and when a fail address for selecting the normal decoder within one of the plurality of banks is registered in the mapping memory, the normal decoder is replaced with the mapping spare decoder within one of the banks associated with the mapping memory. ### Claim 6 (depends on 5) A semiconductor memory according to claim 5, wherein the plurality of banks are accessed substantially simultaneously at the time of a write/read operation. ### Claim 7 (depends on 5) A semiconductor memory according to claim 5, wherein the mapping data is structured by bank data for specifying one of the plurality of banks and spare decoder data for specifying the mapping spare decoder within the one specified bank. ### Claim 8 (depends on 5) A semiconductor memory according to claim 5, further comprising: a specification decoder for specifying one of the plurality of banks and for specifying the mapping spare decoder within the one specified bank, based on the mapping data; and a fail address coincidence detector for comparing an input address with the fail address, and activating the specification decoder when both addresses coincide with each other. ### Claim 9 (depends on 8) A semiconductor memory according to claim 8, wherein the specification decoder is connected to the plurality of banks by a plurality of signal lines, and activates one of the plurality of signal lines connected to one bank specified by the mapping data. ### Claim 10 (depends on 9) A semiconductor memory according to claim 9, further comprising a logic circuit for inactivating the normal decoder within the one bank specified by the mapping data. ### Claim 11 (depends on 5) A semiconductor memory according to claim 5, further comprising: a specification decoder for specifying one of the plurality of banks based on the mapping data; a fail address coincidence detector for comparing an input address with the fail address, and activating the specification decoder when both addresses coincide with each other; and a logic circuit for specifying the mapping spare decoder within the one bank specified by the mapping data. ### Claim 12 (depends on 11) A semiconductor memory according to claim 11, wherein the specification decoder is connected to the plurality of banks by a plurality of signal lines, and activates one of the plurality of signal lines connected to one bank specified by the mapping data. ### Claim 13 (depends on 12) A semiconductor memory according to claim 12, further comprising a logic circuit for inactivating the normal decoder within the one bank specified by the mapping data. ### Claim 14 (depends on 5) A semiconductor memory according to claim 5, wherein the bank having the normal decoder specified by the fail address among the plurality of banks is the same as the bank having the mapping spare decoder associated with the mapping memory among the plurality of banks. ### Claim 15 (depends on 5) A semiconductor memory according to claim 5, wherein the bank having the normal decoder specified by the fail address among the plurality of banks is different from the bank having the mapping spare decoder associated with the mapping memory among the plurality of banks. ### Claim 16 (depends on 5) A semiconductor memory according to claim 5, wherein when the normal decoder is connected to one word line, both the fixed spare decoder and the mapping spare decoder are connected to one spare word line. ### Claim 17 (depends on 5) A semiconductor memory according to claim 5, wherein when the normal decoder is connected to n (n is a plural number) word lines, both the fixed spare decoder and the mapping spare decoder are connected to n spare word lines. ### Claim 18 (depends on 5) A semiconductor memory according to claim 5, wherein the fixed memory and the mapping memory are structured by nonvolatile memories respectively. ### Claim 19 A semiconductor memory comprising: a plurality of banks, each bank having a normal decoder, a fixed spare decoder for relieving the normal decoder, a fixed memory disposed in association with the fixed spare decoder, and at least one mapping spare decoder for relieving the normal decoder; and at least one mapping memory disposed at the outside of the plurality of banks, with no association with a mapping spare decoder, and for being registered with mapping data, wherein the at least one mapping memory is associated with the at least one mapping spare decoder based on the mapping data registered in the at least one mapping memory, and when the number of the plurality of banks is expressed as 2M (M is a natural number), when the number of the at least one mapping spare decoder is expressed as S1 (S1 is a natural number), and also when the number of the at least one mapping memory is expressed as L, the following relationship of 1≦L≦2M×S1 is satisfied. ### Claim 20 A semiconductor memory comprising: a plurality of banks, each bank having a normal decoder, and a mapping spare decoder for relieving the normal decoder; and a mapping memory disposed at the outside of the plurality of banks, and for being registered with mapping data, wherein the mapping data has a function of associating the mapping memory with the mapping spare decoder within one of the plurality of banks, and when a fail address for selecting the normal decoder within one of the plurality of banks is registered in the mapping memory, the normal decoder is replaced with the mapping spare decoder within one of the banks associated with the mapping memory. ### Claim 21 (depends on 20) A semiconductor memory according to claim 20, wherein the plurality of banks are accessed substantially simultaneously at the time of a write/read operation. ### Claim 22 (depends on 20) A semiconductor memory according to claim 20, wherein the mapping data is structured by bank data for specifying one of the plurality of banks and spare decoder data for specifying the mapping spare decoder within the one specified bank. ### Claim 23 (depends on 20) A semiconductor memory according to claim 20, further comprising: a specification decoder for specifying one of the plurality of banks and for specifying the mapping spare decoder within the one specified bank, based on the mapping data; and a fail address coincidence detector for comparing an input address with the fail address, and activating the specification decoder when both addresses coincide with each other. ### Claim 24 (depends on 23) A semiconductor memory according to claim 23, wherein the specification decoder is connected to the plurality of banks by a plurality of signal lines, and activates one of the plurality of signal lines connected to one bank specified by the mapping data. ### Claim 25 (depends on 24) A semiconductor memory according to claim 24, further comprising a logic circuit for inactivating the normal decoder within the one bank specified by the mapping data. ### Claim 26 (depends on 20) A semiconductor memory according to claim 20, further comprising: a specification decoder for specifying one of the plurality of banks based on the mapping data; a fail address coincidence detector for comparing an input address with the fail address, and activating the specification decoder when both addresses coincide with each other; and a logic circuit for specifying the mapping spare decoder within the one bank specified by the mapping data. ### Claim 27 (depends on 26) A semiconductor memory according to claim 26, wherein the specification decoder is connected to the plurality of banks by a plurality of signal lines, and activates one of the plurality of signal lines connected to one bank specified by the mapping data. ### Claim 28 (depends on 27) A semiconductor memory according to claim 27, further comprising a logic circuit for inactivating the normal decoder within the one bank specified by the mapping data. ### Claim 29 (depends on 20) A semiconductor memory according to claim 20, wherein the bank having the normal decoder specified by the fail address among the plurality of banks is the same as the bank having the mapping spare decoder associated with the mapping memory among the plurality of banks. ### Claim 30 (depends on 20) A semiconductor memory according to claim 20, wherein the bank having the normal decoder specified by the fail address among the plurality of banks is different from the bank having the mapping spare decoder associated with the mapping memory among the plurality of banks. ### Claim 31 (depends on 20) A semiconductor memory according to claim 20, wherein when the normal decoder is connected to one word line, both the fixed spare decoder and the mapping spare decoder are connected to one spare word line. ### Claim 32 (depends on 20) A semiconductor memory according to claim 20, wherein when the normal decoder is connected to n word lines (n is a plural number), both the fixed spare decoder and the mapping spare decoder are connected to n spare word lines. ### Claim 33 (depends on 20) A semiconductor memory according to claim 20, wherein the fixed memory and the mapping memory are structured by nonvolatile memories respectively. ### Claim 34 A semiconductor memory comprising: a plurality of banks, each bank having a normal decoder, and at least one mapping spare decoder for relieving the normal decoder; and at least one mapping memory disposed at the outside of the plurality of banks, independent of a mapping spare decoder, and for being registered with mapping data, wherein the at least one mapping memory is associated with the at least one mapping spare decoder based on the mapping data registered in the at least one mapping memory, and when the number of the plurality of banks is expressed as 2M (M is a natural number), when the number of the at least one mapping spare decoder is expressed as S1 (S1 is a natural number), and also when the number of the at least one mapping memory is expressed as L, the following relationship of 1≦L≦2M×S1 is satisfied. ### Claim 35 (depends on 1) A semiconductor memory according to claim 1, wherein the fixed spare decoder and the mapping spare decoder are connected to one spare column select line respectively, when the normal decoder is connected to one column select line. ### Claim 36 (depends on 1) A semiconductor memory according to claim 1, wherein the fixed spare decoder and the mapping spare decoder are connected to n (n is a plural number) spare column select lines respectively, when the normal decoder is connected to n column select lines. ### Claim 37 (depends on 5) A semiconductor memory according to claim 5, wherein when the normal decoder is connected to one column select line, both the fixed spare decoder and the mapping spare decoder are connected to one spare column select line. ### Claim 38 (depends on 5) A semiconductor memory according to claim 5, wherein when the normal decoder is connected to n (n is a plural number) column select lines, both the fixed spare decoder and the mapping spare decoder are connected to n spare column select lines. ### Claim 39 (depends on 20) A semiconductor memory according to claim 20, wherein when the normal decoder is connected to one column select line, both the fixed spare decoder and the mapping spare decoder are connected to one spare column select line. ### Claim 40 (depends on 20) A semiconductor memory according to claim 20, wherein when the normal decoder is connected to n (n is a plural number) column select lines, both the fixed spare decoder and the mapping spare decoder are connected to n spare column select lines.