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AssigneeLSI Logic Corporation
InventorsIVAN PAVISIC, ALEXANDER ANDREEV, RANKO SCEPANOVIC, ANATOLI BOLOTOV
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Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Designing of the IC's require meeting real-world constraints such as minimization of the circuit area, minimization of wire length within the circuit, and minimization of the time the IC requires to perform its function, referred to as the IC delay. In order to design circuits to meet a given set of requirements, each signal path of the circuit must be analyzed. Because of the large number of the cells and the complex connections, the number of paths is very large and requires much computing power to analyze. Also, some of the paths are not important for the purposes of the operations of the chip and can be discounted during the analysis process. The present invention discloses a method and apparatus used to avoid analyzing non-important paths, referred to as false paths of a directed timing graph. To avoid the false paths, the timing graph representing the circuit is modified to exclude the false paths before the graph is analyzed. To modify the timing graph, duplicate nodes are constructed, duplicate edges are constructed, and some edges of the original graph are cut and replaced by mixed edges connecting non-duplicate nodes to duplicate nodes. Finally, mixed edges are created to connect duplicate nodes to non-duplicate nodes, integrating the duplicate graph with the original graph.
A method of modifying timing graph to avoid false paths, said method comprising the step of modifying the timing graph to include all the paths except the false paths.
A method of modifying timing graphs to avoid false interval, PI, said method comprising the steps of:
A method for determining arrival times of pins of an integrated circuit, said method comprising the steps of:
An integrated circuit having pins wherein arrival times of the pins are determined by:
An apparatus for of modifying timing graphs to avoid false paths, said apparatus comprising:
An apparatus for of modifying timing graphs to avoid false interval, PI, said apparatus comprising:
An apparatus for determining arrival times of pins of an integrated circuit, said apparatus comprising:
A machine-readable storage medium containing instructions for a processor, said instructions comprising the steps for the processor to modify the timing graph to include all the paths except the false paths.
Dependencies are inferred from the claim text.