Arithmetic unit performing cyclic redundancy check at high speed
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorMasahiko Ishiwaki
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Abstract
A hold circuit holds results of processing in an arithmetic circuit collectively receiving four bits from inputs. The inventive arithmetic unit collectively processes an input data string, which has generally been processed bit by bit, by four bits at a time, whereby a CRC arithmetic operation can be speeded up. More preferably, the arithmetic unit can flexibly deal with change of a generating polynominal set in the arithmetic circuit when rendering set data corresponding to the generating polynomial changeable.
Claims9
A CRC arithmetic unit for performing error detection of a cyclic redundancy check system on object data on the basis of a generating polynomial, comprising:
- a main arithmetic circuit sequentially receiving a plurality of split data obtained by splitting signal bits included in said object data into a plurality of bits for performing arithmetic processing according to said generating polynomial,
- said main arithmetic circuit performing said arithmetic processing on first data included in said plurality of split data and second data obtained by performing said arithmetic processing on part of said object data received before receiving said first data and generating third data;
- and
- a hold circuit supplying said second data to said main arithmetic circuit and thereafter holding said third data as said second data.
Dependencies are inferred from the claim text.