Data processor with multi-command instruction words

A data processor that addresses instructions as groups of commands which may contain more than one branch command, the data processor comprising

• a command selection unit for selecting an expected taken branch command from the branch commands in a group;
• a target selection unit for selecting a tentative target for the expected taken branch command, the data processor tentatively redirecting control flow to a further group of commands identified by the tentative target, the target selection unit containing an associative target memory for storing targets of previously executed branch commands, the target memory having a set of locations for storing associations, each of a target and an associative address capable of identifying a command in the group, the target selection unit selecting the tentative target on the basis of a match between the associative address associated with the tentative target and an indication of the expected taken command.