Speculative address translation for processor using segmentation and optional paging

In a system having both a segmentation unit and a paging unit for translating physical addresses from virtual addresses, said virtual addresses including a segment identifier and segment offset, the improvement wherein:

• the segmentation unit includes a segment descriptor memory selectable by said segment identifier, said memory capable of storing at least the following:
• I) linear address information describing the base of the segment,
• ii) linear address information describing the base of the segment, and
• iii) physical address information relating to said segment.

A circuit for storing address translation information in a computer system, said computer using both segmentation and paging to translate a virtual address having a segment identifier and segment offset into a physical address, said circuit comprising:

• a segment descriptor memory selectable by said segment identifier, said memory capable of storing at least the following:
• I) linear address information describing the base of the segment,
• ii) linear address information describing the limit of the segment, and
• iii) page frame describing at least a portion of a physical address of said segment.

An address translation system for translating a virtual address having a segment identifier and an offset field into a physical address, said address translation system being used in a computer system and comprising:

• (a) a segmentation unit for generating linear address information based on the virtual address information, and for storing first physical address information having a first physical page frame and a first physical page offset;
• (b) a paging unit coupled to the segmentation unit for generating said first physical page frame and second physical address information having a second physical page frame and a second page offset;
• and
• © a said segmentation unit further including:
• [1] a segment descriptor memory, selectable by said segment identifier of said virtual address, and capable of storing
• I) linear address information describing the base of the segment,
• ii) linear address information describing the limit of the segment,
• iii) said first physical page frame;
• [2] a limit comparator for comparing whether the offset field exceeds the limit of the segment;
• wherein a system memory access can be made by said computer system based on said first physical address information.

A system for address translation in a CPU comprising:

• a) an instruction set employing virtual addresses for accessing data or instructions located at physical addresses in a memory subsystem, said virtual addresses containing a segment identifier field selecting a segment and a segment offset field selecting an offset within the selected segment;
• b) a segmentation circuit for generating linear addresses based on the virtual addresses, and for storing physical address information, said segmentation circuit including at least one segment descriptor memory selectable by said segment identifier, said segment descriptor memory capable of storing:
• (I) segment data describing a segment, said segment data including linear address information describing the base and limit of the segment in a linear address space;
• (ii) a physical address information corresponding to a page frame;
• c) a paging circuit for receiving the linear addresses and generating physical addresses, said paging circuit including a page cache, said page cache optionally storing page frame and page offset field information for said CPU;
• and
• d) a bus interface, capable of coupling the segmentation and paging circuits of the CPU to the memory subsystem, and for performing memory accesses in response to physical address information from either of said segmentation and paging circuits.

An address translation system for translating a virtual address having a segment and an offset field into a physical address, said address translation system being used in a computer system and comprising:

• a) a segmentation unit for generating linear address information based on the virtual address information, and for generating and storing a physical address including a page frame and a page offset, said segmentation unit further including:
• b) [1] a segment descriptor memory, selectable by said segment identifier of said virtual address, and capable of storing
• I) linear address information describing the base of the segment,
• ii) linear address information describing the limit of the segment,
• iii) said page frame;
• [2] a physical address memory for storing said physical address including said page frame number and a page offset;
• and
• wherein an access to a memory subsystem can be made by said computer system based on said physical address.

A method of calculating physical addresses from virtual addresses, said method comprising:

• a) calculating a first physical address, having a first page frame field and a first page offset field, based on a virtual address;
• b) storing said first page frame field of said first physical address;
• c) calculating a second physical address based on a second virtual address including a second page frame field and a second page offset field;
• d) generating a third physical address based on the first page frame field and the second page offset field;
• e) generating a memory access request based on said third physical address.