Logic emulation processor and module unit thereof

A logic emulation processor comprising:

• module units interconnected in said logic emulation processor, each of which includes one or more than one unit combination circuit processor having a plurality of input signals and a plurality of output signals and emulating a combination circuit model or memory model, a plurality of control processors each having a plurality of input signals and one or more than one output signal and operating to generate said input signals to said unit combination circuit processor and emulate a sequential circuit model, and a plurality of multiplexers each receiving said output signals of said unit combination circuit processor, selecting a signal in demand of a control processor, and delivering the selected signal to said control processor;
• means for interconnecting said module units of M in number based on a complete network;
• and
• means for grouping signals to be transferred among said module units into a maximum of M-1 sets of signals and transferring said divided signal sets via a plurality of paths through the neighboring module units.

A logic emulation processor comprising:

• module units interconnected in said logic emulation processor, each of which includes one or more than one unit combination circuit processor having a plurality of input signals and a plurality of output signals and emulating a combination circuit model or memory model, a plurality of control processors each having a plurality of input signals and one or more than one output signal and operating to generate said input signals to said unit combination circuit processor and emulate a sequential circuit model, and a plurality of multiplexers each receiving said output signals of said unit combination circuit processor, selecting a signal in demand of a control processor, and delivering the selected signal to said control processor;
• means for connecting one of said module unit to other neighboring module units of N in number through buses based on an N-dimensional hypercube;
• and
• means for grouping signals to be transferred among said module units into a maximum of N sets of signals, implementing a first procedure of determining immediate transfer paths of N in number from a message sending module having a node address of P=Pn−1Pn−2 . . . P1P0 to a message receiving module having a node address of D=Dn−1Dn−2 . . . D1D0 (the node address is a unique binary number given to each module unit) by inverting the node address P at one bit position at a time thereby to obtain Qn−1=(not Pn−1) Pn−2 . . . P1P0, Qn−2=Pn−1 (not Pn−2 . . . P1P0, . . . , Q1=Pn−1Pn−2 . . . (not P1)P0, and Q0=Pn−1Pn−2 . . . P1 (not P0), implementing a second procedure of taking exclusive logical sums between Qn−1 through Q0 and D for individual bits thereby to obtain Rn−1 through R0, implementing a third procedure, which is repeatedly for values of i of n−1 through 0, of inverting Qi at a same bit position as Ri having a value of “1” sequentially by scanning through the bits downward from the (i−1) th bit position of Ri (from the (n−1)th bit position in the case of i=1) thereby to determine a path from Qi to D, and transferring said divided signal sets from P to D by using the determined paths of N in number.