Semiconductor processing methods of forming integrated circuitry, forming conductive lines, forming a conductive grid, forming a conductive network, forming an electrical interconnection to a node location forming an electrical interconnection with a transistor source/drain region, and integrated circuitry

A method of forming an electrical connection comprising:

• forming a diffusion region in semiconductive material, the diffusion region having an outer surface;
• forming a conductive line laterally spaced from the semiconductive material and diffusion region, a predominate portion of the conductive line being disposed elevationally below the diffusion region outer surface;
• and
• interconnecting the conductive line and the diffusion region with electrically conductive material.

A method of forming at least one interconnection to a node location in SOI integrated circuitry comprising:

• forming a conductive diffused node location in a silicon-containing structure, the structure being formed over and surrounded by isolation oxide;
• forming a first conductive material laterally adjacent the silicon-containing structure, a predominate portion of the first conductive material being disposed elevationally below the diffused node location;
• and
• forming a second conductive material over at least a portion of the first conductive material and the node location to provide an electrical interconnection therebetween.

A method of forming integrated circuitry comprising:

• forming a diffusion region within semiconductive material between spaced apart isolation oxide regions;
• forming a conductive line within at least one of the isolation oxide regions adjacent the diffusion region;
• and
• forming conductive material over the diffusion region and the conductive line to provide an electrical interconnection therebetween.

A method of forming an electrical connection to a node location comprising:

• forming at least one isolation trench within a bulk semiconductive substrate, the isolation trench being disposed laterally adjacent a substrate active area;
• filling the one isolation trench with isolation oxide;
• removing some of the isolation oxide from the one isolation trench;
• replacing the removed isolation oxide with first conductive material;
• forming a diffusion region in the substrate active area, the diffusion region defining a node location to which electrical connection is to be made;
• and
• forming second conductive material over the first conductive material and the diffusion region to provide an electrical connection therebetween.

A method of forming conductive lines comprising:

• forming an oxide isolation grid between semiconductive material;
• forming conductive material within the oxide isolation grid to form a conductive grid therein;
• and
• removing selected portions of the conductive material grid to define interconnect lines within the oxide isolation grid.

A method of forming a conductive grid over a substrate comprising:

• forming a layer of insulative material over a substrate surface;
• forming a plurality of upstanding silicon-containing structures over the insulative material, the silicon-containing structures comprising respective outer surfaces;
• defining a network of conduits within the insulative material between individual silicon-containing structures;
• and
• filling the conduits at least partially with conductive material to provide a conductive grid.

A method of forming conductive lines in electrical contact with active area diffusion regions comprising:

• forming insulative material over a semiconductive substrate;
• forming a plurality of silicon-containing structures over the insulative material, individual silicon-containing structures having respective sidewalls, adjacent silicon-containing structure sidewalls defining respective spaces therebetween;
• forming nitride-containing caps atop the individual silicon-containing structures,
• forming insulative material in the spaces between individual adjacent silicon-containing structures;
• planarizing the insulative material to be generally coplanar with the nitride-containing caps
• etching at least some of the insulative material between individual adjacent silicon-containing structures to a degree sufficient to expose the respective sidewalls of the adjacent silicon-containing structures, the etching defining respective troughs between the sidewalls having lateral widths in lateral width directions;
• depositing an oxide lining material within the troughs and over respective sidewalls to a degree sufficient to fill about two thirds of the lateral width of the trough in the lateral width direction;
• forming conductive material over the substrate and in at least some of the remaining one third of the lateral width of the trough;
• planarizing the oxide lining material and the conductive material to be substantially coplanar with nitride-containing caps;
• recessing remaining conductive material within the trough to below an immediately adjacent planar surface;
• masking selected substrate areas;
• removing conductive material from unmasked substrate areas;
• forming insulative material over the substrate, the insulative material filling in the troughs from which conductive material was removed and covering conductive material which was not removed;
• planarizing the insulative material to be substantially coplanar with the nitride-containing caps;
• removing the nitride-containing caps to outwardly expose respective outer surfaces of the silicon-containing structures, respective outer surfaces defining individual active areas in which diffusion regions are to be formed;
• forming individual oxide layers over respective silicon-containing structure outer surfaces;
• forming a polysilicon layer over the oxide layers;
• planarizing the polysilicon layer;
• forming an oxide layer over the polysilicon layer to provide stack structures over the silicon-containing structures;
• patterning and etching the stack structures to form individual gate structures over the silicon-containing structures;
• forming sidewall spacers over respective gate structure sidewalls;
• forming diffusion regions in the silicon-containing structures adjacent individual gate structures;
• forming insulative material over the substrate;
• planarizing the insulative material;
• patterning and etching the insulative material to outwardly expose at least one diffusion region and at least some of the conductive material;
• and
• forming connective polysilicon material over the one exposed diffusion region and the conductive material, the connective material interconnecting the one exposed diffusion region and the conductive material, the conductive material providing a conductive line to the one diffusion region.

Integrated memory circuitry comprising:

• a substrate;
• a plurality of source/drain diffusion regions supported by the substrate;
• a plurality of isolation oxide regions supported by the substrate and interposed between and separating at least some of the source/drain diffusion regions;
• and
• a plurality of conductive lines supported by the substrate at least some of which being operatively connected with at least some of the source/drain diffusion regions and disposed within the isolation oxide regions.