Asymmetrical MOS channel structure with drain extension

In the fabrication of N+/P+ Dual Poly Gate CMOS transistors, a method for forming asymmetric channel regions, and drain extension regions comprising the steps of:

• a) isolating a regions of silicon, from which a source, a drain, and a channel region between the source and drain, are subsequently formed, and doping the regions;
• b) forming gate electrode regions overlying the silicon region, each gate electrode region having a length extending from the source to the drain, and vertical sidewalls adjoining the source and drain;
• c) forming the channel region in the NMOS transistors by implanting ions of dopant at a predetermined angle, defined from the gate electrode vertical sidewall adjacent the source, into the silicon region underlying the gate to form a channel region having a length less than the gate length, extending from underneath the gate electrode vertical sidewall directly adjacent the source, toward the drain, while simultaneously forming the drain extension region in the PMOS transistors by implanting ions of dopant at a predetermined angle, defined from the gate electrode vertical sidewall adjacent the drain, into the silicon region underlying the gate to form a drain extension extending from underneath the gate electrode vertical sidewall directly adjacent the drain, toward the source;
• and
• d) forming the drain extension in NMOS transistors by implanting ions of dopant at a predetermined angle, defined from the gate electrode vertical sidewall adjacent the drain, into the silicon region underlying the gate to form the drain extension region extending from underneath the gate electrode vertical sidewall directly adjacent the drain, toward the source, while simultaneously forming the channel region in the PMOS transistors by implanting ions of dopant at a predetermined angle, defined from the gate electrode vertical sidewall adjacent the source, into the silicon region underlying the gate to form a channel region having a length less than the gate length, extending from underneath the gate electrode vertical sidewall directly adjacent the source, toward the drain, whereby a transistor is formed with a high breakdown voltage and low source resistance.

A N+/P+ Dual Poly Gate CMOS transistor having asymmetric short channel regions, and drain extension regions comprising:

• isolated silicon regions including a source and a drain;
• gate electrodes overlying said silicon regions having a length extending from said source to said drain, and including vertical sidewalls adjoining said source and drain;
• a silicon channel region having a channel length less than said gate length, underlying said gate and extending from underneath said gate electrode vertical sidewall adjoining said source, toward said drain, said channel region formed by implanting ions of dopant at a predetermined angle, defined from said gate electrode vertical sidewall adjacent said source, into said channel region;
• and
• a silicon drain extension region extending underneath said gate from said drain, toward said channel region, said drain extension region formed by implanting ions of dopant at a predetermined angle, defined from said gate electrode vertical sidewall adjacent said drain, into said drain extension region, whereby said short channel region minimizes drain capacitance, and said lightly doped drain extension maximizes drain operation voltage.

A MOS transistor, selected from the group consisting of NMOS and PMOS transistors, having an asymmetric short channel region and a drain extension region comprising:

• an isolated silicon region including a source and a drain;
• a gate electrode overlying said silicon region having a length extending from said source to said drain, and including vertical sidewalls adjoining said source and drain;
• a silicon channel region having a channel length less than said gate length, underlying said gate and extending from underneath said gate electrode vertical sidewall adjoining said source, toward said drain, said channel region formed by implanting ions of dopant at a predetermined angle, defined from said gate electrode vertical sidewall adjacent said source, into said channel region;
• and
• a silicon drain extension region extending underneath said gate from said drain, toward said channel region, said drain extension region formed by implanting ions of dopant at a predetermined angle, defined from said gate electrode vertical sidewall adjacent said drain, into said drain extension region;
• in which PMOS drain extension regions are formed by implanting a third dopant selected from the group consisting of boron and BF2, in which the third ion dose is in the range between 1×1013 and 1×1015/cm2, in which the third ion energy level is in the range between 2 keV and 30 keV when the dopant is boron, and in which the third ion energy level is in the range between 10 keV and 150 keV when the dopant is BF2;
• and
• in which NMOS drain extension regions are formed by implanting a third dopant selected from the group consisting of phosphorus and arsenic, in which the third ion dose is in the range between 1×1013 and 1×1015/cm2, in which the third ion energy level is in the range between 10 keV and 100 keV when the dopant is phosphorus, and in which the third ion energy level is in the range between 20 keV and 200 keV when the dopant is arsenic, whereby the short channel region minimizes drain capacitance, and a lightly doped drain extension maximizes drain operation voltage.