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US 2001/0019855 A1Published application
Method for manufacturing integrated circuits and semiconductor wafer which has integrated circuits
AssigneeInfineon Technologies AG
InventorHans-Jurgen Hacke
Life of this patent
Estimating the term…
Abstract
A method for manufacturing integrated circuits is described. A semiconductor wafer having an active side with circuit structures is provided. An electrically insulating intermediate layer and an electrically conductive conductor foil are applied to the active side. Conductor tracks with terminal balls are formed with a relatively large spacing pattern in the conductor foil. The semiconductor wafer is subsequently divided up into integrated circuits.
Claims15
A manufacturing method, which comprises the steps of:
- providing a semiconductor wafer having an active side with circuit structures for forming at least two integrated circuits;
- providing at least one electrically insulating intermediate layer;
- applying at least one electrically conductive conductor foil to the electrically insulating intermediate layer;
- forming at least one through-opening in the electrically insulating intermediate layer, the at least one through-opening extends from an underside of the electrically conductive conductor foil to an underside of the electrically insulating intermediate layer;
- applying the least one electrically insulating intermediate layer having the electrically conductive conductor foil to the active side of the semiconductor wafer;
- forming conductor tracks from the electrically conductive conductor foil;
- and
- dividing the semiconductor wafer into individual integrated circuits.
5 more elements
A manufacturing method, which comprises the steps of:
- providing a semiconductor wafer having an active side with circuit structures for at least two integrated circuits;
- applying at least one electrically insulating intermediate layer to the active side of the semiconductor wafer;
- applying a solder material to contact points provided on the semiconductor wafer using a method selected from the group consisting of electro-deposition methods and electroless deposition methods;
- applying at least one electrically conductive conductor foil to the electrically insulating intermediate layer, an application of the electrically conductive conductor foil to the electrically insulating intermediate layer being provided after an application of the electrically insulating intermediate layer to the active side of the semiconductor wafer;
- forming conductor tracks from the electrically conductive conductor foil;
- and
- dividing the semiconductor wafer into individual integrated circuits.
4 more elements
Dependencies are inferred from the claim text.