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AssigneeKabushiki Kaisha Toshiba
InventorsKazuhiro Shimizu, Riichiro Shirota, Naoki Koido, Seiichi Aritome, Hiroaki Tsunoda, Tadashi Iguchi, Kazuhito Narita, Kunihiro Terasaka, Hirohisa Iizuka
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In a nonvolatile semiconductor memory device, a charge accumulation layer is formed between adjacent two device isolation regions, at least a portion of the charge accumulation layer sandwiched with the device isolation regions has side walls each having a taper angle of 80 degrees or more and less than 90 degrees so that the charge accumulation layer at a lower end has a width wider than that at an upper end, a size of an opening of each of the device isolation regions is 0.25 μm or less, and a gate length of a memory cell is 0.2 μm or less.
A nonvolatile semiconductor memory device in which a plurality of memory cells are arranged in an array-like configuration to constitute a cell array having a plurality of device isolation regions buried by an insulation material in trenches formed in a semiconductor substrate, and a plurality of device forming regions each of which is divided with the device isolation regions, and in which each of the memory cells includes a charge accumulation layer formed via a first gate insulation film on the device forming region, and a control gate formed on the charge accumulation layer via a second gate insulation film,
A nonvolatile semiconductor memory device in which a plurality of memory cells are arranged in an array-like configuration to constitute a cell array including a plurality of device isolation regions buried by an insulation material in trenches formed in a semiconductor substrate, and a plurality of device forming regions each of which is divided with the device isolation regions, and in which each of the memory cells has a charge accumulation layer including a conductive layer formed on a first gate insulation film in the device forming region, the conductive layer has side walls each being arranged in alignment with the device forming region, and a control gate is formed on the charge accumulation layer via a second gate insulation film, wherein:
A nonvolatile semiconductor memory device in which a plurality of memory cells are arranged in an array-like configuration to constitute a cell array having a plurality of device isolation regions buried by an insulation material in trenches formed in a semiconductor substrate, a plurality of device forming regions each of which is divided with the device isolation regions, and in which each of the memory cells has a charge accumulation layer including a conductive layer which is formed on a first gate insulation film in the device forming region, the conductive layer has side walls arranged in alignment with the device forming regions and a control gate is formed on the charge accumulation layer via the second gate insulation film, and the nonvolatile semiconductor memory device has at least one peripheral transistor having a gate electrode formed on the semiconductor substrate via a third gate insulation film thicker than the first gate insulation film, wherein:
Dependencies are inferred from the claim text.