DRAM circuit and method of controlling the same

A DRAM circuit comprising:

• a memory cell;
• a bit line pair;
• a sense amplifier connected to said memory cell via said bit line pair;
• a data line pair;
• and a column switch for connecting said bit line pair to said data line pair corresponding thereto via said sense amplifier, wherein the column switch previously selected is made to be OFF during a write masking operation, and said bit line pair corresponding to said data line pair connected to said column switch is made to be nonconductive.

A DRAM circuit comprising:

• a memory cell;
• a bit line pair;
• a sense amplifier connected to said memory cell via said bit line pair;
• a data line pair;
• and a column switch for connecting said bit line pair to said data line pair corresponding thereto via said sense amplifier, wherein said column switch includes:
• a first switch connected to a column select line and said sense amplifier;
• and a second switch connected to said first switch and said data line pair.

A method of controlling a DRAM circuit which comprises:

• a memory cell;
• a bit line pair;
• a sense amplifier connected to said memory cell via said bit line pair;
• a data line pair;
• and a column switch for connecting said bit line pair to said data line pair corresponding thereto via said sense amplifier, the method comprising the steps of:
• selecting a data line pair for a write masking in a write operation;
• setting each line of the selected data line pair to a first potential;
• and allowing said column switch to be OFF by the first potential of said data line pair.