Clock synchronous semiconductor memory device having a reduced access time

A semiconductor memory device comprising:

• internal control signal generating circuitry responsive to an operation mode instructing signal for generating an internal control pulse signal for performing an operation designated by said operation mode instructing signal,
• said internal control signal generating circuitry including a circuit for providing a difference in at least one of a generation timing and a pulse width between a first internal control pulse signal and a subsequent internal control pulse signal when said operation mode instructing signal is successively applied.