Semiconductor integrated circuit for low-voltage high-speed operation

A method of increasing the speed of a circuit, which includes at least one transistor having a source and a substrate, the circuit being powered by a first supply voltage and a second supply voltage, the method comprising:

• providing a bias voltage having a level outside a voltage range defined by the first supply voltage and the second supply voltage;
• connecting the first supply voltage to the substrate of the transistor;
• and
• connecting the bias voltage to the source of the transistor when a control signal is present.

An apparatus, comprising:

• a first CMOS circuit having a first NMOSFET and a first PMOSFET;
• a second CMOS circuit having a second NMOSFET and a second PMOSFET;
• a first power node coupled to a source terminal of the first NMOSFET;
• a second power node selectively coupled to a source terminal of the second NMOSFET;
• and
• a third power node coupled to source terminals of the first and second PMOSFETs.

A circuit, comprising:

• a supply voltage node;
• a transistor having a source terminal and a substrate terminal;
• and
• a bias voltage generator connectable to the source terminal,
• wherein the first supply voltage node is directly connected to the substrate terminal.

An integrated circuit comprising:

• a first supply voltage node and a second supply voltage node;
• a first gate powered by the first and second supply voltage nodes;
• a second gate powered by the first and second supply voltage nodes and a bias voltage node such that the second gate functions faster than the first gate, the second gate being coupled to an output of the first gate;
• and
• a level shifter connected between the first and second gates, to shift a level of the output of the first gate so that it can effectively operate the second gate.