Low-consumption power-on reset circuit for semiconductor memories
AssigneeSTMicroelectronics S.r.l.
InventorsSalvatore Polizzi, Raffaele Solimene
Life of this patent
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Abstract
A power-on reset circuit connected to a supply line feeding a supply voltage, the circuit including an output terminal supplying a power-on reset signal; a divider connected between the supply line (36) and ground and having an intermediate node supplying a division voltage correlated to the supply voltage; an inverter having an input connected to the intermediate node and an output connected to the output terminal and supplying a reset logic signal; and a deactivation branch coupled to the supply line and the intermediate node. The deactivation branch preventing switching of the power-on reset signal on the output terminal when the supply voltage is higher than a deactivation voltage.
Claims20
A power-on reset circuit for a semiconductor memory, comprising:
- a supply line set to a supply voltage;
- an output terminal supplying a reset logic signal;
- a divider connected between said supply line and a reference potential line and having an intermediate node that supplies a division voltage correlated to said supply voltage and connected to said output terminal;
- and deactivation means coupled to said supply line and said intermediate node, said deactivation means being active and preventing switching of the reset logic signal when said supply voltage is higher than a deactivation voltage, and being inactive when said supply voltage is lower than said deactivation voltage.
A power-on reset circuit, comprising:
- a voltage divider circuit coupled between a ground potential and a supply line supplying a supply voltage, the voltage divider circuit configured to output a division voltage at an intermediate node;
- an inverter coupled between the intermediate node and an output terminal, the inverter configured to output a power-on reset signal when the supply voltage is below a first threshold value;
- and
- a deactivation circuit coupled to the supply line and to the inverter, the deactivation circuit configured to prevent output of the power-on reset signal and to maintain the division voltage at approximately the supply voltage when the supply voltage is above a second threshold voltage.
A power-on reset circuit, comprising:
- a supply line set to a supply voltage;
- a supply circuit coupled to the supply line and configured to generate a division voltage at an intermediate node;
- an inverter connected between the intermediate node and an output terminal and configured to output a power-on reset signal when the supply voltage is less than a threshold value;
- and
- a deactivation circuit coupled to the supply line and the intermediate node, the deactivation circuit configured to prevent output of the power-on reset signal, and to maintain the division voltage at a value that is approximately the value of the supply voltage such that the inverter does not absorb current when the supply voltage is above the threshold value.
Dependencies are inferred from the claim text.