Non-volatile semiconductor memory device and manufacturing method thereof
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKenji Kawai, Hajime Kimura, Kazuyuki Ohmi
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Abstract
A non-volatile semiconductor memory device and a manufacturing method of the same where an etching residue generating short-circuit between gates is made harmless or a device is miniaturized are obtained. The method includes the steps of forming on a semiconductor substrate, a first gate layer and a second gate layer, forming a second gate electrode by etching the second gate layer, forming a first gate electrode by etching the first gate layer using the second gate electrode as a mask, and removing a residue left on a step portion by isotropic etching.
Claims12
A method of manufacturing a non-volatile semiconductor memory device comprising the steps of:
- forming a first gate layer on a main surface of a semiconductor substrate with a first gate insulation film posed therebetween;
- forming a second gate layer on said first gate layer with a second gate insulation film posed therebetween;
- forming a second gate electrode by etching said second gate layer using a resist as a mask;
- forming a first gate electrode by etching said first gate layer using said second gate electrode as a mask;
- and
- performing an isotropic etching on an etching residue left on a side wall of a step formed by an insulation film in contact with a side wall of said first gate layer and said first gate insulation film, after the etching of said first gate layer, to remove the etching residue.
A non-volatile semiconductor memory device comprising:
- a first gate insulation film formed on a main surface of a semiconductor substrate;
- a first gate electrode formed thereon;
- a second gate electrode formed on said first gate electrode with a second gate insulation film posed therebetween;
- and
- a protective film on a side wall of said second gate electrode.
A non-volatile semiconductor memory device comprising:
- a first gate lower electrode formed on a main surface of a semiconductor substrate with a first gate insulation film posed therebetween;
- a first interlayer insulation film thicker than the first gate lower electrode and defining width of said first gate lower electrode;
- a second interlayer insulation film formed on said first interlayer insulation film;
- a first gate fin electrode formed on said first gate lower electrode, having a fin portion extending in the periphery of the first interlayer insulation film and along a side wall of the second interlayer insulation film, and making up a first gate electrode together with said first gate lower electrode;
- and
- a second gate electrode formed on said first gate fin electrode with a second gate insulation film posed therebetween.
Dependencies are inferred from the claim text.