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AssigneeHitachi, Ltd.
InventorsToshiaki Yamanaka, Shin?apos; ichiro Kimura, Hideyuki Matsuoka, Tomonori Sekiguchi, Takeshi Sakata, Kiyoo Itoh
Estimating the term…
According to the present invention, an overlay margin is secured for matching a wiring electrode 11 with a storage electrode 15 of a capacitor at their point of contact and the required area for a memory cell can be decreased by placing the plug electrode 11 of titanium nitride in the active region of a semiconductor substrate or over the gate electrode, reducing the size of the opening for passing the storage electrode 15 of the capacitor of a stacked structure, and decreasing the line width of a wiring electrode 13. By the common use of the above-mentioned plug electrodes in a CMISFET region in the peripheral circuit and in a memory cell of a static RAM, their circuit layouts can be made compact.
A semiconductor memory device comprising:
A semiconductor memory device having a memory cell, including a first transistor on a principal surface of a silicon substrate and a first wiring formed by a first metal, said first wiring being laid through a first insulating film and a second insulating film above said first transistor, wherein a first element is formed on said first wiring through a third insulating film, and wherein said first element is connected to said first transistor through a connecting body including a first conductor provided in an opening passing through said first insulating film, and a second conductor provided in an opening passing through said second insulating film and a third insulating film.
A semiconductor device comprising a memory cell including a first transistor provided on a principal surface of a silicon substrate, and a logic circuit including second and third transistors of mutually different conductivity types, wherein on a principal surface of a first insulating film, a plurality of first wirings made of a first metal are formed in a memory cell region and a logic circuit region, wherein said first wirings are connected to said first, second and third transistors by connecting body including said first wiring and passing through said first insulating film, wherein a second insulting film is provided on said first wiring, wherein a first element is provided on a principal surface of said second insulating film in the memory cell region, and wherein said first element is connected to said first transistor by a connecting body including said first conductor and second conductor penetrating into said second insulating film.
A semiconductor integrated circuit device having a first insulating film provided on a principal surface of a semiconductor substrate and a first wiring formed by a conductor filled in a first opening in said first insulating film, wherein insulating side walls formed of other insulating films are deposited on side walls of said first opening of said first insulating film and a line width of said first wiring is defined by said side walls.
A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:
Dependencies are inferred from the claim text.