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US 2001/0018987 A1Published application
Interconnect structure
OwnerGeorge Tzanavaras, Mihalis Michaelinventors
Life of this patent
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Abstract
An embodiment of the present invention is a method for wafer level IC packaging that includes the steps of: (a) forming compliant, conductive bumps on metalized bond pads or conductors; and (b) surrounding the compliant, conductive bumps in a supporting layer.
Claims20
A method for forming interconnects comprises:
- forming compliant, conductive bumps on metalized bond pads or conductors;
- and
- at least partially surrounding the compliant, conductive bumps in a supporting layer.
A method for forming interconnects comprises:
- cleaning vias formed on a wafer;
- filling vias and forming metalized bond pads;
- forming compliant, conductive bumps on the metalized bond pads;
- at least partially surrounding the compliant, conductive bumps in a supporting layer;
- delineating the compliant, conductive bumps;
- forming conductive bumps over the compliant, conductive bumps;
- singulating integrated circuits from the wafer;
- and
- bonding the singulated integrated circuits to a printed circuit board.
6 more elements
A method for forming interconnects comprises:
- cleaning vias formed on a wafer;
- filling vias and forming metalized bond pads;
- forming compliant, conductive bumps on the metalized bond pads;
- at least partially surrounding the compliant, conductive bumps in a supporting layer;
- delineating the compliant, conductive bumps;
- forming conductive bumps over the compliant, conductive bumps;
- singulating integrated circuits from the wafer;
- forming compliant, conductive bumps on a printed circuit board;
- at least partially surrounding the compliant, conductive bumps in a supporting layer;
- bonding the singulated integrated circuits to the printed circuit board.
7 more elements
Dependencies are inferred from the claim text.