Method of physical design for integrated circuit

A method of physical design for an integrated circuit made up of multiple cells, the method comprising the steps of:

• a) evaluating the overall performance of the integrated circuit;
• b) selecting, as a candidate cell that should have its performance changed, at least one of the cells from the integrated circuit based on a result of the step a);
• and
• c) changing the performance of the candidate cell selected in the step b),
• wherein the steps a), b) and c) are performed repeatedly, and
• wherein in the step a), one of multiple evaluating approaches prepared is selected on a predetermined condition and the performances of the cells, included in the integrated circuit, are evaluated by the approach selected.

A method of physical design for an integrated circuit made up of multiple cells, the method comprising the steps of:

• a) determining relative positions of the cells and wires interconnecting the cells together in the integrated circuit;
• b) evaluating a performance of the integrated circuit;
• c) selecting, as a candidate cell that should have its performance changed, at least one of the cells from the integrated circuit based on a result of the step b);
• and
• d) changing the performance of the candidate cell selected in the step c),
• wherein the steps b), c) and d) are performed repeatedly, and
• wherein no matter how many times the steps b) through d) are performed, the same relative positions of the cells and wires, determined in the step a), are maintained.

A method of physical design for an integrated circuit made up of multiple cells, the method comprising the steps of:

• a) evaluating the overall performance of the integrated circuit;
• b) selecting, as a candidate cell that should have its performance changed, at least one of the cells from the integrated circuit based on a result of the step a);
• and
• c) changing the performance of the candidate cell selected in the step b),
• wherein the steps a), b) and c) are performed repeatedly, and
• wherein each said cell should have a minimum area initially, and
• wherein in the step c), the performance of the candidate cell is changed by allowing the candidate cell to just increase its area.

A method of physical design for an integrated circuit made up of multiple cells, the method comprising the steps of:

• a) evaluating the overall performance of the integrated circuit;
• b) selecting, as a candidate cell that should have its performance changed, at least one of the cells from the integrated circuit based on a result of the step a);
• and
• c) changing the performance of the candidate cell selected in the step b),
• wherein the steps a), b) and c) are performed repeatedly, and
• wherein in the step a), the size of transistors, which make up each said cell, is optimized with the area and performance of the cell taken into account, and then the performance of the cell, made up of the transistors of the optimized size, is evaluated.