Method of layouting semiconductor integrated circuit and apparatus for doing the same

A method of layouting a semiconductor integrated circuit comprised of a plurality of cells, comprising the steps of:

• (a) inputting first data and second data into an automatic layout system, said first data relating to connection of a circuit, said second data relating to said cells and a fill cell which is to be positioned at a space formed between said cells and includes a protection circuit for preventing a wiring electrically connecting said cells to each other from being charged;
• (b) arranging said cells, based on said first and second data;
• (c) positioning said fill cell in a space formed between said cells;
• (d) checking whether there is caused antenna effect due to said wiring being charged, and transmitting a check signal identifying a wiring which needs to be protected from said antenna effect;
• and
• (e) carrying out a process for preventing said antenna effect, to said wiring identified with said check signal.

An apparatus for layouting a semiconductor integrated circuit comprised of a plurality of cells, comprising:

• (a) a first memory including first data relating to connection of a circuit;
• (b) a second memory including second data relating to said cells and a fill cell which is to be positioned at a space formed between said cells and includes a protection circuit for preventing a wiring electrically connecting said cells to each other from being charged;
• (c) an automatic layout system which arranges said cells, based on said first and second data, and positions said fill cell in a space formed between said cells;
• and
• (d) an electronic design automation tool which checks whether there is caused antenna effect due to said wiring being charged, and transmits a check signal identifying a wiring which needs to be protected from said antenna effect;
• said automatic layout system carrying out a process for preventing said antenna effect, to said wiring identified with said check signal.

A semiconductor integrated circuit comprised of a plurality of cells, comprising:

• (a) a semiconductor substrate including protection elements formed therein, said protection elements each comprising a first diffusion layer formed at a surface of said substrate and a second diffusion layer around said first diffusion layer, said first diffusion layer having a first electrical conductivity and said second diffusion layer having a second electrical conductivity;
• (b) a grounded line electrically connecting to said second diffusion layer through a contact hole;
• (c) a voltage source line electrically connecting to a third diffusion layer formed at a surface of said substrate, through a contact hole, said third diffusion layer having a first electrical conductivity, said grounded line and said voltage source line both being comprised of a first metal wiring layer;
• and
• (d) a target wiring which is comprised of said first metal wiring layer and needs to be protected from antenna effect,
• one of said protection elements being located just below said target wiring, said target wiring being electrically connected to said first diffusion layer of said one of protection elements through a contact hole.

A semiconductor integrated circuit comprised of a plurality of cells, comprising:

• (a) a semiconductor substrate including protection elements formed therein, said protection elements each comprising a first diffusion layer formed at a surface of said substrate and a second diffusion layer around said first diffusion layer, said first diffusion layer having a first electrical conductivity and said second diffusion layer having a second electrical conductivity;
• (b) a grounded line electrically connecting to said second diffusion layer through a contact hole;
• (c) a voltage source line electrically connecting to a third diffusion layer formed at a surface of said substrate, through a contact hole, said third diffusion layer having a first electrical conductivity, said grounded line and said voltage source line both being comprised of a first metal wiring layer;
• (d) a target wiring which is comprised of said first metal wiring layer and needs to be protected from antenna effect, and
• (e) a connector wiring having a first end located just above one of said protection elements located in the vicinity of said target wiring, and a second end at which said connector wiring is electrically connected to said target wiring,
• said connector wiring being electrically connected at said first end to said first diffusion layer of said one of protection elements through a contact hole.

A semiconductor integrated circuit comprised of a plurality of cells, comprising:

• (a) a semiconductor substrate including protection elements formed therein, said protection elements each comprising a first diffusion layer formed at a surface of said substrate and a second diffusion layer around said first diffusion layer, said first diffusion layer having a first electrical conductivity and said second diffusion layer having a second electrical conductivity;
• (b) a grounded line electrically connecting to said second diffusion layer through a contact hole;
• (c) a voltage source line electrically connecting to a third diffusion layer formed at a surface of said substrate, through a contact hole, said third diffusion layer having a first electrical conductivity, said grounded line and said voltage source line both being comprised of a first metal wiring layer;
• (d) a target wiring which is comprised of a second metal wiring layer located above said first metal wiring layer, and which needs to be protected from antenna effect;
• and
• (e) a connector wiring comprised of said first metal wiring layer,
• at least one of said protection elements being located just below said target wiring, said target wiring being electrically connected to said connector wiring through a first contact hole, and said connector wiring being electrically connected to said first diffusion layer of said one of protection elements through a second contact hole.

A semiconductor integrated circuit comprised of a plurality of cells, comprising:

• (a) a semiconductor substrate including protection elements formed therein, said protection elements each comprising a first diffusion layer formed at a surface of said substrate and a second diffusion layer around said first diffusion layer, said first diffusion layer having a first electrical conductivity and said second diffusion layer having a second electrical conductivity;
• (b) a grounded line electrically connecting to said second diffusion layer through a contact hole;
• (c) a voltage source line electrically connecting to a third diffusion layer formed at a surface of said substrate, through a contact hole, said third diffusion layer having a first electrical conductivity, said grounded line and said voltage source line both being comprised of a first metal wiring layer;
• (d) a target wiring which is comprised of a second metal wiring layer located above said first metal wiring layer, and which needs to be protected from antenna effect;
• and
• (e) a connector wiring which is comprised of said first metal wiring layer and which has a first end located just below said target wiring and a second end located just above one of said protection elements,
• said connector wiring being electrically connected at said first end to said target wiring through a first contact hole, and being electrically connected at said second end to said first diffusion layer of said one of protection elements through a second contact hole.

A semiconductor integrated circuit comprising:

• (a) a plurality of macro cells;
• (b) a target wiring which needs to be protected from antenna effect and which electrically connects a driver cell located in one of said macro cells to a gate electrode cell located in another one of said macro cells,
• said target wiring passing through a space defined between said macro cells, said space being filled with fill cells each including a protection circuit for preventing antenna effect,
• said target wiring being electrically connected to a fill cell located closest to said gate electrode cell.