Integrated data clock extractor

A circuit for generating a data clock signal from timing information provided by an input data stream, comprising:

• a programmable delay element for receiving an arbitrary clock signal, delaying said arbitrary clock signal by a variable programmable amount and in response generating an extracted data clock signal;
• and
• a clock phase detector for comparing logic level transitions of said input data stream with transitions of said extracted data clock signal and in response generating a delay adjust signal for defining said variable programmable amount of delay such that the transitions of said input data stream are substantially aligned with the transitions of said arbitrary clock signal, wherein said programmable delay element further comprises:
• a multi-element delay line for receiving and delaying said arbitrary clock signal, said delay line having a plurality of taps for outputting successively incrementally delayed versions of said arbitrary clock signal;
• a first multiplexer for receiving said delay adjust signal and in response selecting one of said taps for outputting said extracted data clock signal;
• and
• a cycle limit extractor for receiving least and most incrementally delayed versions of said arbitrary clock signal and in response calculating lower and upper limit values for initializing said clock phase detector to generate a correct delay adjust signal in the event that either said variable programmable amount is to be decremented and said least incrementally delayed version of said arbitrary clock signal is being output by said multi-element delay line or said variable programmable amount is to be incremented and said most incrementally delayed version of said arbitrary clock signal is being output by said multi-element delay line, respectively.