Array-type processor
AssigneeNEC Corporation
InventorsTaro Fujii, Masato Motomura, Koichiro Furuta
Life of this patent
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Abstract
To execute all processing in an array section of an array-type processor, each processor must execute processing of different types, i.e., processing of an operating unit and processing of a random logic circuit, which limits its size and processing performance. A data path section including processors arranged in an array are connected via programmable switches to primarily execute processing of operation and a state transition controller configured to easily implement a state transition function to control state transitions are independently disposed. These sections are configured in customized structure for respective processing purposes to efficiently implement and achieve the processing of operation and the control operation.
Claims33
An array-type processor, comprising:
- a state transition control section including
- a state transition table memory for storing a state transition table in which transition rules between a plurality of operation states are written, and
- a sequencer section for controlling, using the state transition table memory, transitions between the operation states and for determining the operation states at a particular point of time;
- and
- a data path section independent of said state transition control section, including
- a plurality of processor elements for executing processing of operations according to the operation states determined by said state transition control section, and
- a plurality of programmable switch elements for connecting the processor elements to each other according to the operation states determined by said state transition control section,
- said processor elements and said programmable switch elements being electrically connected in a two-dimensional array shape, wherein:
- each said processor element includes
- an instruction code memory for storing a plurality of instruction codes,
- an instruction decoder for decoding an instruction code read from said instruction code memory, and
- an operating section for executing processing of operation according to the instruction code decoded by said instruction decoder;
- and
- each said programmable switch element includes a connection layout information memory for storing a plurality of sets of connection layout information, the information indicating a connection layout between said processor elements and said programmable switch elements and/or between said programmable switch elements.
Dependencies are inferred from the claim text.