Memory management device and memory management method thereof

A memory management device comprising:

• memory region size storing means for storing a size of a predetermined-size readable and writable memory region,
• first memory size storing means for storing a size of a fixed-length block as a first memory cell which divides a memory region of a size stored in the memory region size storing means,
• a first bit map unit for storing a state of use of each said first memory cell in said memory region as a bit map indicative any of at least three states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use and “in use” indicating a state where all the memory cell is in use,
• second to a-th bit map units for, when each N times, which is a predetermined integral multiple, the memory amount of said first memory cell is grouped into a higher-order memory cell and each N times the memory amount of the higher-order memory cell is further grouped into a further higher-order memory cell to layer said memory region to have (a−1) layers (a:
• integer not less than 2) as the maximum layer and set these memory cells as the second to a-th memory cells, storing a state of use of each memory cell as a bit map indicative any of at least three states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use and “in use” indicating a state where all the memory cell is in use,
• memory cell layer selecting means for, upon a request for ensuring memory in said memory region, selecting a layer of a memory cell whose size is smaller than and most approximate to the requested memory size,
• address searching means for searching a bit map unit corresponding to a memory cell of a layer selected by the memory cell layer selecting means for an address indicative of a place at which one or a plurality of successive memory cells exist where data equivalent to the size of said memory requested to be ensured can be successively stored, with a memory cell at said state of “not in use” or “partly in use” as a leading address,
• memory ensuring means for ensuring said memory region equivalent to the minimum number of successive memory cells necessary for satisfying the size of said memory requested to be ensured by using an address searched by the address searching means, and
• bit map unit changing means for changing states of a bit map corresponding to a memory cell ensured by the memory ensuring means and a bit map corresponding to a memory cell whose layer is higher than the layer of the ensured memory cell and whose state is subjected to a change into “partly in use” or “in use” according to the state obtained after the change.

A memory management device comprising:

• memory region size storing means for storing a size of a predetermined-size readable and writable memory region,
• first memory size storing means for storing a size of a fixed-length block as a first memory cell which divides a memory region of a size stored in the memory region size storing means,
• a first bit map unit for storing a state of use of each said first memory cell in said memory region as a bit map indicative any of four states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use, “in use” indicating a state where all the memory cell is in use, and “head of allocation” indicating the head of a memory cell where data of a requested memory size is stored,
• second to a-th bit map units for, when each N times, which is a predetermined integral multiple, the memory amount of said first memory cell is grouped into a higher-order memory cell and each N times the memory amount of the higher-order memory cell is further grouped into a further higher-order memory cell to layer said memory region to have (a−1) layers (a:
• integer not less than 2) as the maximum layer and set these memory cells as the second to a-th memory cells, storing a state of use of each memory cell as a bit map indicative any of four states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use, “in use” indicating a state where all the memory cell is in use, and “head of allocation” indicating the head of a memory cell where data of a requested memory size is stored,
• memory cell layer selecting means for, upon a request for ensuring memory in said memory region, selecting a layer of a memory cell whose size is smaller than and most approximate to the requested memory size,
• address searching means for searching a bit map unit corresponding to a memory cell of a layer selected by the memory cell layer selecting means for an address indicative of a place at which one or a plurality of successive memory cells exist where data equivalent to the size of said memory requested to be ensured can be successively stored, with a memory cell at said state of “not in use” or “partly in use” as a leading address,
• memory ensuring means for ensuring said memory region equivalent to the minimum number of successive memory cells necessary for satisfying the size of said memory requested to be ensured by using an address searched by the address searching means, and
• bit map unit changing means for changing a bit map corresponding to a memory cell ensured by the memory ensuring means into “partly in use”, “in use” or “head of allocation”, as well as changing a state of a bit map corresponding to a memory cell whose layer is higher than the layer of the ensured memory cell and whose state is subjected to a change into “partly in use” or “in use” according to the state obtained after the change.

A memory management device comprising:

• memory region size storing means for storing a size of a predetermined-size readable and writable memory region,
• first memory size storing means for storing a size of a fixed-length block as a first memory cell which divides a memory region of a size stored in the memory region size storing means,
• a first bit map unit for storing a state of use of each said first memory cell in said memory region as a bit map indicative any of four states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use, “in use” indicating a state where all the memory cell is in use, and “head of allocation” indicating the head of a memory cell where data of a requested memory size is stored,
• second to a-th bit map units for, when each N times, which is a predetermined integral multiple, the memory amount of said first memory cell is grouped into a higher-order memory cell and each N times the memory amount of the higher-order memory cell is further grouped into a further higher-order memory cell to layer said memory region to have (a−1) layers (a:
• integer not less than 2) as the maximum layer and set these memory cells as the second to a-th memory cells, storing a state of use of each memory cell as a bit map indicative any of four states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use, “in use” indicating a state where all the memory cell is in use, and “head of allocation” indicating the head of a memory cell where data of a requested memory size is stored,
• one-order higher layer memory cell selecting means for, upon a request for ensuring memory in said memory region, determining whether there exists a memory cell whose size is relatively close to and larger than the requested memory size,
• first memory cell layer selecting means for, when the one-order higher layer memory cell selecting mean determines that there exists no memory cell satisfying the condition, selecting a layer of a memory cell whose size is smaller and most approximate to the requested memory size,
• second memory cell layer selecting means for, when said one-order higher layer memory cell selecting mean determines that there exists a memory cell satisfying the condition, selecting the memory cell of the layer,
• address searching means for searching a bit map unit corresponding to a memory cell of a layer selected by said first or second memory cell layer selecting means for an address indicative of a place at which one or a plurality of successive memory cells exist where data equivalent to the size of said memory requested to be ensured can be successively stored, with a memory cell at said state of “not in use” or “partly in use” as a leading address,
• memory ensuring means for ensuring said memory region equivalent to the minimum number of successive memory cells necessary for satisfying the size of said memory requested to be ensured by using an address searched by the address searching means, and
• bit map unit changing means for changing a bit map corresponding to a memory cell ensured by the memory ensuring means into “partly in use”, “in use” or “head of allocation”, as well as changing a state of a bit map corresponding to a memory cell whose layer is higher than the layer of the ensured memory cell and whose state is subjected to a change into “partly in use” or “in use” according to the state obtained after the change.

A memory management device comprising:

• memory region size storing means for storing a size of a predetermined-size readable and writable memory region,
• first memory size storing means for storing a size of a fixed-length block as a first memory cell which divides a memory region of a size stored in the memory region size storing means,
• a first bit map unit for storing a state of use of each said first memory cell in said memory region as a bit map indicative any of four states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use, “in use” indicating a state where all the memory cell is in use, and “head of allocation” indicating the head of a memory cell where data of a requested memory size is stored,
• second to a-th bit map units for, when each N times, which is a predetermined integral multiple, the memory amount of said first memory cell is grouped into a higher-order memory cell and each N times the memory amount of the higher-order memory cell is further grouped into a further higher-order memory cell to layer said memory region to have (a−1) layers (a:
• integer not less than 2) as the maximum layer and set these memory cells as the second to a-th memory cells, storing a state of use of each memory cell as a bit map indicative any of four states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use, “in use” indicating a state where all the memory cell is in use, and “head of allocation” indicating the head of a memory cell where data of a requested memory size is stored,
• memory cell selecting means for, upon a request for ensuring memory in said memory region, selecting a combination of memory cells satisfying said requested memory size by combining a memory cell whose size is smaller than and most approximate to the requested memory size and a memory cell of a further smaller size,
• address searching means for searching a bit map unit corresponding to a memory cell of each layer selected by the memory cell selecting means for an address indicative of a place at which one or a plurality of successive memory cells exist where data equivalent to the size of said memory requested to be ensured can be successively stored, with a memory cell at said state of “not in use” or “partly in use” as a leading address,
• memory ensuring means for ensuring said memory region equivalent to the minimum number of successive memory cells necessary for satisfying the size of said memory requested to be ensured by using an address searched by the address searching means, and
• bit map unit changing means for changing a bit map corresponding to a memory cell ensured by the memory ensuring means into “partly in use”, “in use” or “head of allocation”, as well as changing a state of a bit map corresponding to a memory cell whose layer is higher than the layer of the ensured memory cell and whose state is subjected to a change into “partly in use” or “in use” according to the state obtained after the change.

A memory management device comprising:

• memory region size storing means for storing a size of a predetermined-size readable and writable memory region,
• first memory size storing means for storing a size of a fixed-length block as a first memory cell which divides a first memory region obtained by dividing a memory region of a size stored in the memory region size storing means in half at a predetermined address as a boundary,
• a first bit map unit for storing a state of use of each said first memory cell in said first memory region as a bit map indicative any of four states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use, “in use” indicating a state where all the memory cells is in use, and “head of allocation” indicating the head of a memory cell where data of a requested memory size is stored,
• second to a-th bit map units for, when each N times, which is a predetermined integral multiple, the memory amount of said first memory cell is grouped into a higher-order memory cell and each N times the memory amount of the higher-order memory cell is further grouped into a further higher-order memory cell to layer said memory region to have (a−1) layers (a:
• integer not less than 2) as the maximum layer and set these memory cells as the second to a-th memory cells, allocating these memory cells to said first memory region and a remaining second memory region and storing a state of use of each memory cell corresponding to the first and the second memory regions as a bit map,
• memory cell layer selecting means for, upon a request for ensuring memory in said memory region, selecting a layer of a memory cell whose size is smaller than and most approximate to the requested memory size,
• address searching means for searching a bit map unit corresponding to a memory cell of a layer selected by the memory cell layer selecting means for an address indicative of a place at which the minimum number of successive memory cells exist necessary for satisfying the size of said memory requested to be ensured, and
• memory ensuring means for ensuring said memory region equivalent to the minimum number of successive memory cells necessary for satisfying the size of said memory requested to be ensured by using an address searched by the address searching means.

A memory management device comprising:

• memory region size storing means for storing a size of a predetermined-size readable and writable memory region,
• first memory size storing means for storing a size of a fixed-length block as a first memory cell which divides a first memory region obtained by dividing a memory region of a size stored in the memory region size storing means in half at a predetermined address as a boundary,
• a first bit map unit for storing a state of use of each said first memory cell in said first memory region as a bit map,
• second to a-th bit map units for, when each N times, which is a predetermined integral multiple, the memory amount of said first memory cell is grouped into a higher-order memory cell and each N times the memory amount of the higher-order memory cell is further grouped into a further higher-order memory cell to layer said memory region to have (a−1) layers (a:
• integer not less than 2) as the maximum layer and set these memory cells as the second to a-th memory cells, representing a state of use of each memory cell as any of four states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use, “in use” indicating a state where all the memory cell is in use, and “head of allocation” indicating the head of a memory cell where data of a requested memory size is stored, allocating these memory cells to said first memory region and a remaining second memory region and storing a state of use of each memory cell corresponding to the first and the second memory regions as a bit map,
• memory cell selecting means for, upon a request for ensuring memory in said memory region, selecting a combination of memory cells satisfying said requested memory size by combining a memory cell whose size is smaller than and most approximate to the requested memory size and a memory cell of a further smaller size,
• address searching means for searching a bit map unit corresponding to a memory cell of each layer selected by the memory cell selecting means for an address indicative of a place at which one or a plurality of successive memory cells exist where data equivalent to the size of said memory requested to be ensured can be successively stored, with a memory cell at said state of “not in use” or “partly in use” as a leading address,
• memory ensuring means for ensuring said memory region equivalent to the minimum number of successive memory cells necessary for satisfying the size of said memory requested to be ensured by using an address searched by the address searching means, and
• bit map unit changing means for changing a bit map corresponding to a memory cell ensured by the memory ensuring means into “partly in use”, “in use” or “head of allocation”, as well as changing a state of a bit map corresponding to a memory cell whose layer is higher than the layer of the ensured memory cell and whose state is subjected to a change into “partly in use” or “in use” according to the state obtained after the change.

A memory management method comprising:

• a memory region size storing step of storing a size of a predetermined-size readable and writable memory region,
• a first memory size storing step of storing a size of a fixed-length block as a first memory cell which divides a memory region of a size stored at the memory region size storing step,
• a first bit map unit storing step of storing a state of use of each said first memory cell in said memory region as a bit map,
• a second to a-th bit map unit storing step of, when each N times, which is a predetermined integral multiple, the memory amount of said first memory cell is grouped into a higher-order memory cell and each N times the memory amount of the higher-order memory cell is further grouped into a further higher-order memory cell to layer said memory region to have (a−1) layers (a:
• integer not less than 2) as the maximum layer and set these memory cells as the second to a-th memory cells, storing a state of use of each memory cell as a bit map,
• a memory cell layer selecting step of, upon a request for ensuring memory in said memory region, selecting a layer of a memory cell whose size is smaller than and most approximate to the requested memory size,
• an address searching step of searching a bit map unit corresponding to a memory cell of a layer selected by the memory cell layer selecting step for an address indicative of a place at which the minimum number of successive memory cells exist necessary for satisfying the size of said memory requested to be ensured, and
• a memory ensuring step of ensuring said memory region equivalent to the minimum number of successive memory cells necessary for satisfying the size of said memory requested to be ensured by using an address searched by the address searching step.

A memory management method comprising:

• a memory region size storing step for storing a size of a predetermined-size readable and writable memory region,
• a first memory size storing step of storing a size of a fixed-length block as a first memory cell which divides a memory region of a size stored at the memory region size storing step,
• a first bit map unit storing step of storing a state of use of each said first memory cell in said memory region as a bit map indicative any of at least three states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use and “in use” indicating a state where all the memory cell is in use,
• a second to a-th bit map unit storing step of, when each N times, which is a predetermined integral multiple, the memory amount of said first memory cell is grouped into a higher-order memory cell and each N times the memory amount of the higher-order memory cell is further grouped into a further higher-order memory cell to layer said memory region to have (a−1) layers (a:
• integer not less than 2) as the maximum layer and set these memory cells as the second to a-th memory cells, storing a state of use of each memory cell as a bit map indicative any of at least three states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use and “in use” indicating a state where all the memory cell is in use,
• a memory cell layer selecting step of, upon a request for ensuring memory in said memory region, selecting a layer of a memory cell whose size is smaller than and most approximate to the requested memory size,
• an address searching step of searching a bit map unit corresponding to a memory cell of a layer selected by the memory cell layer selecting step for an address indicative of a place at which one or a plurality of successive memory cells exist where data equivalent to the size of said memory requested to be ensured can be successively stored, with a memory cell at said state of “not in use” or “partly in use” as a leading address,
• a memory ensuring step of ensuring said memory region equivalent to the minimum number of successive memory cells necessary for satisfying the size of said memory requested to be ensured by using an address searched by the address searching step, and
• a bit map unit changing step of changing states of a bit map corresponding to a memory cell ensured by the memory ensuring step and a bit map corresponding to a memory cell whose layer is higher than the layer of the ensured memory cell and whose state is subjected to a change into “partly in use” or “in use” according to the state obtained after the change.

A memory management method comprising:

• a memory region size storing step of storing a size of a predetermined-size readable and writable memory region,
• a first memory size storing step of storing a size of a fixed-length block as a first memory cell which divides a memory region of a size stored in the memory region size storing step,
• a first bit map unit storing step of storing a state of use of each said first memory cell in said memory region as a bit map indicative any of four states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use, “in use” indicating a state where all the memory cell is in use, and “head of allocation” indicating the head of a memory cell where data of a requested memory size is stored,
• a second to a-th bit map unit storing step of, when each N times, which is a predetermined integral multiple, the memory amount of said first memory cell is grouped into a higher-order memory cell and each N times the memory amount of the higher-order memory cell is further grouped into a further higher-order memory cell to layer said memory region to have (a−1) layers (a:
• integer not less than 2) as the maximum layer and set these memory cells as the second to a-th memory cells, storing a state of use of each memory cell as a bit map indicative any of four states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use, “in use” indicating a state where all the memory cell is in use, and “head of allocation” indicating the head of a memory cell where data of a requested memory size is stored,
• a memory cell layer selecting step of, upon a request for ensuring memory in said memory region, selecting a layer of a memory cell whose size is smaller than and most approximate to the requested memory size,
• an address searching step of searching a bit map unit corresponding to a memory cell of a layer selected by the memory cell layer selecting step for an address indicative of a place at which one or a plurality of successive memory cells exist where data equivalent to the size of said memory requested to be ensured can be successively stored, with a memory cell at said state of “not in use” or “partly in use” as a leading address,
• a memory ensuring step of ensuring said memory region equivalent to the minimum number of successive memory cells necessary for satisfying the size of said memory requested to be ensured by using an address searched by the address searching step, and
• a bit map unit changing step of changing a bit map corresponding to a memory cell ensured by the memory ensuring step into “partly in use”, “in use” or “head of allocation”, as well as changing a state of a bit map corresponding to a memory cell whose layer is higher than the layer of the ensured memory cell and whose state is subjected to a change into “partly in use” or “in use” according to the state obtained after the change.

A memory management method comprising:

• a memory region size storing step of storing a size of a predetermined-size readable and writable memory region,
• a first memory size storing step of storing a size of a fixed-length block as a first memory cell which divides a memory region of a size stored at the memory region size storing step,
• a first bit map unit storing step of storing a state of use of each said first memory cell in said memory region as a bit map indicative any of four states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use, “in use” indicating a state where all the memory cell is in use, and “head of allocation” indicating the head of a memory cell where data of a requested memory size is stored,
• a second to a-th bit map unit storing step of, when each N times, which is a predetermined integral multiple, the memory amount of said first memory cell is grouped into a higher-order memory cell and each N times the memory amount of the higher-order memory cell is further grouped into a further higher-order memory cell to layer said memory region to have (a−1) layers (a:
• integer not less than 2) as the maximum layer and set these memory cells as the second to a-th memory cells, storing a state of use of each memory cell as a bit map indicative any of four states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use, “in use” indicating a state where all the memory cell is in use, and “head of allocation” indicating the head of a memory cell where data of a requested memory size is stored,
• a one-order higher layer memory cell selecting step of, upon a request for ensuring memory in said memory region, determining whether there exists a memory cell whose size is relatively close to and larger than the requested memory size,
• a first memory cell layer selecting step of, when the one-order higher layer memory cell selecting step determines that there exists no memory cell satisfying the condition, selecting a layer of a memory cell whose size is smaller and most approximate to the requested memory size,
• a second memory cell layer selecting step of, when said one-order higher layer memory cell selecting step determines that there exists a memory cell satisfying the condition, selecting the memory cell of the layer,
• an address searching step of searching a bit map unit corresponding to a memory cell of a layer selected by said first or second memory cell layer selecting step for an address indicative of a place at which one or a plurality of successive memory cells exist where data equivalent to the size of said memory requested to be ensured can be successively stored, with a memory cell at said state of “not in use” or “partly in use” as a leading address,
• a memory ensuring step of ensuring said memory region equivalent to the minimum number of successive memory cells necessary for satisfying the size of said memory requested to be ensured by using an address searched by the address searching step, and
• a bit map unit changing step of changing a bit map corresponding to a memory cell ensured by the memory ensuring step into “partly in use”, “in use” or “head of allocation”, as well as changing a state of a bit map corresponding to a memory cell whose layer is higher than the layer of the ensured memory cell and whose state is subjected to a change into “partly in use” or “in use” according to the state obtained after the change.

A memory management method comprising:

• a memory region size storing step of storing a size of a predetermined-size readable and writable memory region,
• a first memory size storing step of storing a size of a fixed-length block as a first memory cell which divides a memory region of a size stored at the memory region size storing step,
• a first bit map unit storing step of storing a state of use of each said first memory cell in said memory region as a bit map indicative any of four states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use, “in use” indicating a state where all the memory cell is in use, and “head of allocation” indicating the head of a memory cell where data of a requested memory size is stored,
• a second to a-th bit map unit storing step of storing, when each N times, which is a predetermined integral multiple, the memory amount of said first memory cell is grouped into a higher-order memory cell and each N times the memory amount of the higher-order memory cell is further grouped into a further higher-order memory cell to layer said memory region to have (a−1) layers (a:
• integer not less than 2) as the maximum layer and set these memory cells as the second to a-th memory cells, storing a state of use of each memory cell as a bit map indicative any of four states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use, “in use” indicating a state where all the memory cell is in use, and “head of allocation” indicating the head of a memory cell where data of a requested memory size is stored,
• a memory cell selecting step of, upon a request for ensuring memory in said memory region, selecting a combination of memory cells satisfying said requested memory size by combining a memory cell whose size is smaller than and most approximate to the requested memory size and a memory cell of a further smaller size,
• an address searching step of searching a bit map unit corresponding to a memory cell of each layer selected by the memory cell selecting step for an address indicative of a place at which one or a plurality of successive memory cells exist where data equivalent to the size of said memory requested to be ensured can be successively stored, with a memory cell at said state of “not in use” or “partly in use” as a leading address,
• a memory ensuring step of ensuring said memory region equivalent to the minimum number of successive memory cells necessary for satisfying the size of said memory requested to be ensured by using an address searched at the address searching step, and
• a bit map unit changing step of changing a bit map corresponding to a memory cell ensured by the memory ensuring step into “partly in use”, “in use” or “head of allocation”, as well as changing a state of a bit map corresponding to a memory cell whose layer is higher than the layer of the ensured memory cell and whose state is subjected to a change into “partly in use” or “in use” according to the state obtained after the change.

A memory management method comprising:

• a memory region size storing step of storing a size of a predetermined-size readable and writable memory region,
• a first memory size storing step of storing a size of a fixed-length block as a first memory cell which divides a first memory region obtained by dividing a memory region of a size stored at the memory region size storing step in half at a predetermined address as a boundary,
• a first bit map unit storing step of storing a state of use of each said first memory cell in said first memory region as a bit map indicative any of four states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use, “in use” indicating a state where all the memory cell is in use, and “head of allocation” indicating the head of a memory cell where data of a requested memory size is stored,
• a second to a-th bit map unit storing step of, when each N times, which is a predetermined integral multiple, the memory amount of said first memory cell is grouped into a higher-order memory cell and each N times the memory amount of the higher-order memory cell is further grouped into a further higher-order memory cell to layer said memory region to have (a−1) layers (a:
• integer not less than 2) as the maximum layer and set these memory cells as the second to a-th memory cells, allocating these memory cells to said first memory region and a remaining second memory region and storing a state of use of each memory cell corresponding to the first and the second memory regions as a bit map,
• a memory cell layer selecting step of, upon a request for ensuring memory in said memory region, selecting a layer of a memory cell whose size is smaller than and most approximate to the requested memory size,
• an address searching step of searching a bit map unit corresponding to a memory cell of a layer selected by the memory cell layer selecting step for an address indicative of a place at which the minimum number of successive memory cells exist necessary for satisfying the size of said memory requested to be ensured, and
• a memory ensuring step of ensuring said memory region equivalent to the minimum number of successive memory cells necessary for satisfying the size of said memory requested to be ensured by using an address searched by the address searching step.

A memory management method comprising:

• a memory region size storing step of storing a size of a predetermined-size readable and writable memory region,
• a first memory size storing step of storing a size of a fixed-length block as a first memory cell which divides a first memory region obtained by dividing a memory region of a size stored at the memory region size storing step in half at a predetermined address as a boundary,
• a first bit map unit storing step of storing a state of use of each said first memory cell in said first memory region as a bit map,
• a second to a-th bit map unit storing step of, when each N times, which is a predetermined integral multiple, the memory amount of said first memory cell is grouped into a higher-order memory cell and each N times the memory amount of the higher-order memory cell is further grouped into a further higher-order memory cell to layer said memory region to have (a−1) layers (a:
• integer not less than 2) as the maximum layer and set these memory cells as the second to a-th memory cells, representing a state of use of each memory cell as any of four states of “not in use” indicating a state where a memory cell is not in use, “partly in use” indicating a state where a memory cell is partly in use, “in use” indicating a state where all the memory cell is in use, and “head of allocation” indicating the head of a memory cell where data of a requested memory size is stored, allocating these memory cells to said first memory region and a remaining second memory region and storing a state of use of each memory cell corresponding to the first and the second memory regions as a bit map,
• a memory cell selecting step of, upon a request for ensuring memory in said memory region, selecting a combination of memory cells satisfying said requested memory size by combining a memory cell whose size is smaller than and most approximate to the requested memory size and a memory cell of a further smaller size,
• an address searching step of searching a bit map unit corresponding to a memory cell of each layer selected by the memory cell selecting step for an address indicative of a place at which one or a plurality of successive memory cells exist where data equivalent to the size of said memory requested to be ensured can be successively stored, with a memory cell at said state of “not in use” or “partly in use” as a leading address,
• a memory ensuring step of ensuring said memory region equivalent to the minimum number of successive memory cells necessary for satisfying the size of said memory requested to be ensured by using an address searched at the address searching step, and
• a bit map unit changing step of changing a bit map corresponding to a memory cell ensured at the memory ensuring step into “partly in use”, “in use” or “head of allocation”, as well as changing a state of a bit map corresponding to a memory cell whose layer is higher than the layer of the ensured memory cell and whose state is subjected to a change into “partly in use” or “in use” according to the state obtained after the change.