Power-saving mode for portable communication devices

In combination with at least two communication devices packaged in a single portable unit having a single battery providing power for operating said devices, a power management unit comprising:

• an oscillator producing a clock signal;
• an inverter including a P-channel FET having a gate coupled to said clock signal and a channel coupling a first output terminal to an output node, and an N-channel FET having a gate coupled to said clock signal and a channel coupling a second output terminal to said output node;
• a current-limiting resistor;
• an intermediate FET having a gate and a channel in series with said current-limiting resistor coupling a first output terminal to a second output terminal;
• a plurality of series-coupled diodes coupling said output node to the gate of said intermediate FET;
• a flyback inductor through which current from a storage device intermittently flows being controlled by said intermediate FET for providing intermittent output power subsequent to rectification and filtering powers a second communication device;
• an intermediate node interposed between a current-limiting resistor and an intermediate FET;
• a final FET having a gate coupled to said intermediate node through at least one buffer, said final FET and said flyback inductor providing a serial current path between said first and second output terminals;
• and
• a final node within the serial current path, said final node interposed between said flyback inductor and said final FET for said intermittent output power being taken from the final node.

In combination with a wireless communication device and a pager device packaged in a single portable unit having a single battery providing power for operating both of said devices, a power management unit comprising:

• an oscillator producing a clock signal;
• an inverter having both a P-channel FET having a gate coupled to said clock signal and a channel coupling a first output terminal to an output node and an N-channel FET having a gate coupled to said clock signal and a channel coupling a second output terminal to said output node;
• a current-limiting resistor;
• an intermediate FET having a gate and a channel connected in series with said current-limiting resistor coupling a first output terminal to a second output terminal;
• a plurality of series-coupled diodes coupling said output node to the gate of said intermediate FET;
• and
• a flyback inductor through which current from a storage device intermittently flows being controlled by said intermediate FET to provide intermittent output power subsequent to the rectification and filtering thereof powers said second communication device.