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US 2001/0017814 A1Published application
Semiconductor integrated circuit device with test interface circuit for performing test on embedded memory from outside
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKazutami Arimoto, Hiroki Shimano
Life of this patent
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Abstract
A first test clock signal and a second test clock signal are generated from a common basic test clock signal using a delay line with a changeable delay time and a delay stage with a fixed delay time. A memory circuit is operated in synchronization with one of the first and second test clock signals, and the memory circuit is provided with a signal/data according to the other test clock signal. Thus, the set-up time and the hold time of a signal for the memory can be measured with accuracy in a memory-merged system LSI.
Claims13
A semiconductor integrated circuit device, comprising:
- a clock circuit for generating a first clock signal and a second clock signal according to a basic clock signal;
- a memory circuit operating in synchronization with one of said first clock signal and said second clock signal and according to a received operation designation;
- and
- a control transfer circuit for applying said operation designation to said memory circuit in response to other of said first clock signal and said second clock signal.
1 more element
Dependencies are inferred from the claim text.