Negative voltage generating circuit with high control responsiveness which can be formed using transistor with low breakdown voltage and semiconductor memory device including the same
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorFukashi Morishita
Life of this patent
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Abstract
A voltage generating circuit of the present invention includes a charge pump regulator and a voltage converting circuit. Charge pump regulator receives Ext.Vcc and a ground voltage as inputs and outputs a negative voltage Vbb1. Charge pump regulator receives Int.Vcc and negative voltage Vbb1 as inputs and outputs negative voltage Vbb2(<Vbb1). Voltage converting circuit receives Int.Vcc and negative voltage Vbb2 as inputs and outputs an output voltage Vnn. In each of charge pump regulator, a voltage difference between the input and the output is designed such that it is equal to or lower than a prescribed value determined by a size of a transistor.
Claims17
A voltage generating circuit generating a negative output voltage in accordance with a negative reference voltage, comprising:
- a voltage converting circuit driven by a first voltage higher than said output voltage and a second negative voltage lower than said output voltage for generating said output voltage following said negative reference voltage;
- and
- an sub-voltage generating circuits supplying said second negative voltage and including first to m-th sub-voltage generating circuits each driven by a corresponding first driving voltage equal to or lower than a ground voltage and equal to or higher than said second negative voltage and by a corresponding second driving voltage for generating a corresponding internal negative voltage,
- said first sub-voltage generating circuit receiving the ground voltage as said corresponding first driving voltage and a third positive voltage as said corresponding second driving voltage for generating and controlling a first internal negative voltage so as to maintain a difference between said first internal negative voltage and said third positive voltage within a prescribed value,
- said i-th sub-voltage generating circuit (2≦i≦m) receiving an (i−1)th internal negative voltage generated by said (i−1)th sub-voltage generating circuit as said corresponding first driving voltage and an (i+2)th positive voltage as said corresponding second driving voltage for generating and controlling an i-th internal negative voltage so as to maintain a difference between said i-th internal negative voltage and said (i+2)th positive voltage within said prescribed value, and
- said m-th sub-voltage generating circuit generating said second negative voltage as said m-th internal negative voltage.
A semiconductor memory device inputting and outputting a storage data in accordance with an address signal, comprising:
- a memory cell array having a plurality of memory cells arranged in a matrix;
- a word line provided for every row of said memory cell;
- row selecting means selectively activating said word line in accordance with said address signal;
- and
- a voltage generating circuit generating a negative output voltage used for inactivation of said word line in accordance with a negative reference voltage corresponding to an inactivation state of said word line, said voltage generating circuit further including:
- a first power supply line supplying said first voltage;
- a second power supply line supplying said second negative voltage;
- an output line transmitting said output voltage;
- differential amplification circuit supplied with current from said first and second power supply lines for outputting a voltage deviation signal in accordance with a difference between said output voltage and said negative reference voltage;
- and
- a current control circuit controlling a current flow between said second power supply line and said output line according to the level of said voltage deviation signal.
Dependencies are inferred from the claim text.