Semiconductor memory device allowing static-charge tolerance test between bit lines
AssigneeFujitsu Limited
InventorShinya Fujioka
Life of this patent
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Abstract
A semiconductor memory device includes bit lines which transfer data of memory cells, a plurality of first sense amplifier circuits connected to odd-number lines of the bit lines, a plurality of second sense amplifier circuits connected to even-number lines of the bit lines, and a clamp-voltage generation circuit which supplies a first clamp voltage to the first sense amplifier circuits, and supplies a second clamp voltage to the second sense amplifier circuits, whereby during test operation, the odd-number lines are clamped to the first clamp voltage, and the even-number lines are clamped to the second clamp voltage.
Claims10
A semiconductor memory device, comprising:
- bit lines which transfer data of memory cells;
- a plurality of first sense amplifier circuits connected to odd-number lines of said bit lines;
- a plurality of second sense amplifier circuits connected to even-number lines of said bit lines;
- and
- a clamp-voltage generation circuit which supplies a first clamp voltage to said first sense amplifier circuits, and supplies a second clamp voltage to said second sense amplifier circuits, whereby during test operation, the odd-number lines are clamped to the first clamp voltage, and the even-number lines are clamped to the second clamp voltage.
A semiconductor memory device, comprising:
- bit lines;
- and
- a clamp-voltage generation circuit which generates first and second clamp voltages, wherein during test operation, odd-number lines of said bit lines are clamped to the first clamp voltage, and even-number lines of said bit lines are clamped to the second clamp voltage.
Dependencies are inferred from the claim text.