Semiconductor device, semiconductor memory device and test-mode entry method
AssigneeFujitsu Limited
InventorShigemasa Ito
Life of this patent
Estimating the term…
Abstract
A semiconductor device for reliably detecting an erroneous entry into a test mode in ordinary usage and for performing various operational tests at the time of shipment includes an internal circuit and a test-mode control circuit. The test-mode control circuit includes a first control circuit and a second control circuit. The test-mode control circuit operates the internal circuit in the test mode in accordance with a test mode command. The first control circuit inactivates at least a part of the internal circuit in accordance with the test mode command. The second control circuit activates at least the part of the internal circuit in accordance with a release command supplied following the test mode command.
Claims8
A semiconductor device comprising:
- an internal circuit operated in accordance with a plurality of operation modes including a test mode;
- and
- a test-mode control circuit, connected to the internal circuit, for operating the internal circuit in the test mode in accordance with a test mode command,
- the test-mode control circuit including:
- a first control circuit, connected to the internal circuit, for inactivating at least a part of the internal circuit in accordance with the test mode command, and a second control circuit, connected to the first control circuit, for activating at least the part of the internal circuit inactivated by the first control circuit in accordance with a release command supplied following the test mode command.
A semiconductor memory device comprising:
- an internal circuit operated in accordance with a plurality of operation modes including a test mode, a data write mode and a data read mode, the internal circuit including an input/output circuit having a data input/output terminal;
- a first control circuit, connected to the internal circuit, for setting the internal circuit to the test mode and inactivating at least a part of the input/output circuit in accordance with a first command signal for setting the test mode;
- and
- a second control circuit, connected to the internal circuit, for activating at least the part of the input/output circuit inactivated by the first control circuit in accordance with a second command signal supplied following the first command signal, thereby ensuring data input/output in the test mode.
A method of entering a test mode in a semiconductor device which has a plurality of operation modes including a test mode, operates in accordance with a plurality of operation commands, and has an internal circuit, the method comprising the steps of:
- entering the test mode in accordance with a test mode command to be supplied to the semiconductor device;
- inactivating at least a part of the internal circuit;
- activating at least the part of the inactivated internal circuit in accordance with a release command supplied following the test mode command;
- and
- executing a data write mode and a data read mode in the test mode.
Dependencies are inferred from the claim text.