Semiconductor device and semiconductor device testing method
AssigneeFujitsu Limited
InventorsYasuhiro Okumura, Yoshitaka Takahashi, Akihiro Funyu
Life of this patent
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Abstract
A semiconductor device has a normal mode and a test mode for testing the semiconductor device, and is provided with a first circuit which receives an input signal, a test signal and an output enable signal, and outputs the input signal in response to the output enable signal, a second circuit which is coupled to the first circuit and outputs the input signal obtained from the first circuit, and power supply pads which receive a power supply voltage which is supplied in common to the first circuit and the second circuit. The first circuit fixes an output impedance of the second circuit to a high-impedance regardless of the output enable signal when the test signal indicates the test mode.
Claims6
A semiconductor device having a normal mode and a test mode for testing the semiconductor device, comprising:
- a first circuit which receives an input signal, a test signal and an output enable signal, and outputs the input signal in response to the output enable signal;
- a second circuit which is coupled to said first circuit and outputs the input signal obtained from said first circuit;
- and
- power supply pads which receive a power supply voltage which is supplied in common to said first circuit and said second circuit,
- said first circuit fixing an output impedance of said second circuit to a high-impedance regardless of the output enable signal when the test signal indicates the test mode.
A semiconductor device testing method for testing a semiconductor device in a test mode, said semiconductor device also having a normal mode and being constructed to supply a common power supply voltage to first and second circuits thereof which are mutually coupled, said semiconductor device testing method comprising the steps of:
- (a) controlling the first circuit to output an input signal to the second circuit in response to an output enable signal when a test signal indicates the normal mode;
- and
- (b) measuring a current at an arbitrary node within the first circuit in a state where an output impedance of the second circuit is fixed to a high-impedance, regardless of the output enable signal, when the test signal indicates the test mode.
Dependencies are inferred from the claim text.