Semiconductor memory device for distributing load of input and output lines

A semiconductor memory device for distributing load of input and output lines, comprising:

• a line pre-charging means for pre-charging a global read line composed of a pair of lines to a high level in an initial or steady state;
• a plurality of memory banks connected to a global write line composed of a pair of lines for storing data provided thereto, each of which includes a memory cell array composed of a number of memory cells coupled to a multiplicity of sense amplifiers and the multiplicity of write drivers, wherein said multiplicity of amplifiers amplifies data signals from the memory cells to provide it through a read line composed of a pair of lines to a read line driver which provides the data on said read line to said global read line on a read operation, and said multiplicity of write drivers are connected through a write line composed of a pair of lines to said write line driver for storing the data on said global write line into the memory cells;
• a plurality of multiplexers for selecting the data from said read line;
• and
• a data input means for providing externally inputted data to said global write line on the write operation.