Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless of whether a preceding address and a present address match each other

A semiconductor storage device conducting a late-write operation, the device comprising:

• an address compare circuit comparing a preceding address corresponding to a preceding write-operation and a present address corresponding to a present read-operation so as to determine whether said preceding address and said present address match each other;
• and
• a control circuit controlling a normal read-operation to read data from a memory core circuit when said preceding address and said present address do not match each other, controlling a normal read-operation to read data not from said memory core circuit but from a data latch circuit when said preceding address and said present address match each other, and controlling a test read-operation to read data from said memory core circuit regardless of whether said preceding address and said present address match each other.

A semiconductor storage device having a function to mask one of higher order bits and lower order bits of all bits of data to be written in a normal write-operation, the device comprising:

• a mask control circuit capable of masking all the bits of the data in a test write-operation.