Synchronous semiconductor memeory device and method for reading data
AssigneeFujitsu Limited
InventorJun Watanabe
Life of this patent
Estimating the term…
Abstract
A synchronous semiconductor memory device for switching an output route of read data based on latency information includes a read amplifier, a register block, a first signal route, a second signal route, and a switching circuit. The read amplifier amplifies the data read from a memory cell. The register block latches the amplified data and outputs the latched data at a timing corresponding to latency information. The first signal route is connected to the read amplifier to bypass the register block. The second signal route is connected to the read amplifier via the register block. The switching circuit is connected to the first and second signal routes and outputs either the amplified data or the latched data.
Claims13
A synchronous semiconductor memory device comprising:
- memory cells for storing data;
- a read amplifier connected to the memory cells for amplifying data read from one of the memory cells to generate an amplified read data signal;
- a register block connected to the read amplifier for receiving the amplified read data signal in response to a clock signal to generate a latched read data signal, wherein the register block outputs the latched read data signal based on latency information;
- and
- a switching control circuit connected to the register block for outputting one of the amplified read data signal and the latched read data signal based on the latency information, wherein the switching control circuit outputs the amplified read data signal when a value of the latency information is set to one.
A synchronous semiconductor memory device comprising:
- memory cells for storing data;
- a read amplifier connected to the memory cells for amplifying data read from one of the memory cells to generate an amplified read data signal;
- a register block connected to the read amplifier for receiving the amplified read data signal in response to a clock signal to generate a latched read data signal, wherein the register block outputs the latched read data signal based on latency information;
- a control circuit for generating a switch control signal based on the latency information;
- a first signal route connected to the read amplifier to bypass the register block;
- a second signal route connected to the read amplifier via the register block;
- and
- a switching circuit connected to the first and second routes for outputting one of the amplified read data signal and the latched read data signal.
A method for reading data stored in memory cells of a synchronous semiconductor memory device, wherein the semiconductor memory device includes a read amplifier for amplifying data read from one of the memory cells, a register block for receiving the amplified data in response to a clock signal and outputting the latched data based on latency information, a first signal route connected to the read amplifier to bypass the register block, and a second signal route connected to the read amplifier via the register block, the method comprising the steps of:
- selecting one of the first and second signal routes based on the latency information;
- and
- outputting the data associated with the selected signal route.
Dependencies are inferred from the claim text.