Level converter circuit and aliquid crystal display device employing the same

A level converter circuit comprising:

• an input terminal adapted to be supplied with a digital signal swinging from a first voltage to a second voltage lower than said first voltage;
• a first transistor having a gate electrode connected to said input terminal, and a source electrode connected to ground potential;
• a second transistor having a gate electrode connected to a drain electrode of said first transistor, a source electrode connected to a supply voltage, and a drain electrode connected to an output terminal;
• a load circuit connected between said gate electrode of said second transistor and said supply voltage;
• a third transistor having a source electrode connected to said input terminal, a drain electrode connected to said output terminal, and a gate electrode supplied with a DC voltage higher than said second voltage and lower than said first voltage, wherein
• (a) when said input terminal is supplied with said first voltage, said first transistor and said second transistor are ON, and said level converter circuit outputs a third voltage higher than said first voltage;
• and
• (b) when said input terminal is supplied with said second voltage, said first transistor and said second transistor are OFF and said level converter circuit outputs said second voltage via said third transistor.

A liquid crystal display device including a pair of substrates, a liquid crystal layer sandwiched between said pair of substrates, a plurality of pixels formed between said pair of substrates and a driver circuit for driving said plurality of pixels, said driver circuit being provided with a level converter circuit,

• said level converter circuit comprising:
• an input terminal adapted to be supplied with a digital signal swinging from a first voltage to a second voltage lower than said first voltage;
• a first transistor of an n-channel type having a gate electrode connected to said input terminal, and a source electrode connected to ground potential;
• a second transistor of a p-channel type having a gate electrode connected to a drain electrode of said first transistor, a source electrode connected to a supply voltage, and a drain electrode connected to an output terminal;
• a load circuit connected between said gate electrode of said second transistor and said supply voltage;
• a third transistor having a source electrode connected to said input terminal, a drain electrode connected to said output terminal, and a gate electrode supplied with a DC voltage,
• said DC voltage being such that,
• (a) when said source electrode of said third transistor is supplied with said second voltage, said third transistor is ON, and
• (b) when said source electrode of said third transistor is supplied with said first voltage, said third transistor is OFF, wherein
• (i) said first transistor and said second transistor are ON and said level converter circuit outputs a third voltage higher than said first voltage, when said input terminal is supplied with said first voltage;
• and
• (ii) said first transistor and said second transistor are OFF and said level converter circuit outputs said second voltage via said third transistor, when said input terminal is supplied with said second voltage.