Flat panel display having scanning lines driver circuits and its driving method
AssigneeKabushiki Kaisha Toshiba
InventorsHideyuki Kogure, Kazuo Nakamura
Life of this patent
Estimating the term…
Abstract
The scanning lines driver circuit according to this invention comprises a timing circuit unit to which voltage is supplied from a power source, a level shifter circuit unit that generates voltage for driving pixel switching devices, a plurality of gate voltage sources that connect power sources to the level shifter circuit unit and a gate buffer unit that supplies the output from the level shifter circuit unit to scanning lines. The level shifter circuit unit is a series of flip-flop type level shifter circuits that conduct level shifting for each gate voltage source and transistors controlled by a power source detection circuit are inserted in parallel in the outputs from those level shifter circuits.
Claims11
A scanning lines driver circuit that provides scanning lines driver signals for the scanning lines on active matrix type liquid crystal displays having a plurality of scanning lines, a plurality of image signaling lines crossing orthogonal to these scanning lines and pixel switching devices connected to these scanning lines and image signaling lines, comprising:
- a first voltage source;
- a plurality of gate voltage sources;
- a power source detection circuit;
- transistors controlled by said power source detection circuit;
- a timing generation circuit to which voltage is supplied from said first voltage source;
- a level shifter circuit that is connected to said first voltage source and a plurality of gate voltage sources and generates voltage for driving said image switching devices;
- and
- a gate buffer that supplies the output voltage from said level shifter circuit to said scanning lines;
- wherein said level shifter circuit is made of serially connected flip-flop type level shifter circuits that shift voltage levels for each of said gate voltage sources and said transistors are arranged in parallel with the outputs of said level shifter circuits.
A power-on sequence for the scanning lines driver circuit that provides scanning lines driver signals for the scanning lines on active matrix type liquid crystal displays having a plurality of scanning lines, a plurality of image signaling lines crossing orthogonal to these scanning lines and pixel switching devices connected to these scanning lines and image signaling lines, comprising:
- a first voltage source;
- a plurality of gate voltage sources;
- a power source detection circuit;
- transistors controlled by said power source detection circuit;
- a timing generation circuit to which voltage is supplied from said first voltage source;
- a level shifter circuit that is connected to said first voltage source and a plurality of gate voltage sources and generates voltage for driving said image switching devices;
- and
- a gate buffer that supplies the output voltage from said level shifter circuit to said scanning lines;
- comprising the steps of:
- turning on the first voltage source that enables the operation of the timing generation circuit;
- and
- shifting each gate voltage by turning on each gate voltage in the same order as that of serially connected level shifter circuits.
A scanning lines driver circuit that provides a plurality of scanning lines in sequence with scanning pulses including high and low level voltages, comprising:
- a first level shifter circuit and a second level shifter circuit which are serially connected;
- a first transistor and a second transistor which are connected in parallel to the outputs of said first and second level shifter circuits;
- and
- a power source detection circuit that controls said first and second transistors.
A flat display driving method for the flat panel display having a plurality of signaling and scanning lines, pixel electrodes electrically connected to the signaling lines via switching devices connected to the scanning lines, and a first scanning lines driver circuit and a second scanning lines driver circuit that output in sequence scanning pulses including high and low levels of voltage, comprising the steps of:
- shifting a first standard voltage to a first voltage by a first level shifter circuit;
- and
- controlling the operation of a second level shifter circuit when a second standard voltage is shifted to a second voltage by a second level shifter circuit.
Dependencies are inferred from the claim text.