D-FF circuit
AssigneeAndo Electric Co., Ltd.
InventorKazuo Nakaizumi
Life of this patent
Estimating the term…
Abstract
A D-FF circuit for operating a master flip-flop and a slave flip-flop at each predetermined timing in accordance with a plurality of clock signals generated by a clock signal generating circuit, wherein the clock signal generating circuit generates the plurality of clock signals at different timings, the slave flip-flop starts operating in accordance with a clock signal which is generated at an earlier timing than another clock signal generated by the clock signal generating circuit, and the master flip-flop stops operating in accordance with a clock signal which is generated at a later timing than another clock signal generated by the clock signal generating circuit.
Claims6
A D-FF circuit for operating a master flip-flop and a slave flip-flop at each predetermined timing in accordance with a plurality of clock signals generated by a clock signal generating circuit,
- wherein the clock signal generating circuit generates the plurality of clock signals at different timings,
- the slave flip-flop starts operating in accordance with a clock signal which is generated at an earlier timing than another clock signal generated by the clock signal generating circuit, and
- the master flip-flop stops operating in accordance with a clock signal which is generated at a later timing than another clock signal generated by the clock signal generating circuit.
A D-FF circuit comprising:
- a master flip-flop,
- a slave flip-flop, and
- a clock signal generating circuit for generating at least two clock signals at different timings respectively;
- wherein the slave flip-flop starts operating in accordance with one clock signal which is generated by the clock signal generating circuit earlier than another clock signal, and
- the master flip-flop stops operating in accordance with the another clock signal.
Dependencies are inferred from the claim text.