Integrated circuit comprising an output transistor with a controlled fall time
AssigneeSTMicroelectronics S.r.l.
InventorsBertrand Bertrand, Jean Devin
Life of this patent
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Abstract
An integrated circuit electrically is supplied with a voltage and includes an output MOS transistor having a gate driven by an output of a logic circuit and a circuit for biasing the gate of the output MOS transistor. The circuit for biasing the gate is provided for lowering a gate-source bias voltage of the output MOS transistor in a conductive state in relation to the gate-source bias voltage that would otherwise be provided by the output of the logic circuit. The present invention is particularly applicable to output stages for I2C buses.
Claims12
Method of lengthening the time for passing to zero of a terminal of an output transistor (TOUT) of the MOS type connected to a data transmission line (31) presenting a predetermined electric capacitance (CBUS), while keeping a substantially identical working point (VOL, IOL) in the low state of the transistor (TOUT), the gate of the transistor being driven by a logic circuit (11) present in an integrated circuit (20) receiving a predetermined supply voltage (Vcc), the method being characterized in that it comprises a step of lowering the gate-source bias voltage (VGS) of the transistor in the conductive state in relation to the one (Vcc) which would naturally appear at the output of the logic circuit (11) if such a step was not provided, and a step of designing the transistor consisting in increasing the width over length ratio (W/L) of the gate of the transistor for keeping the initial working point in the low state (VOL, IOL) of the transistor.
Integrated circuit (20, 50) electrically supplied with a predetermined voltage (Vcc) and comprising an output MOS transistor (TOUT), the gate of which is driven by the output of a logic circuit (11), characterized in that it comprises a circuit (41) for biasing the gate of the transistor (TOUT), provided for lowering the gate-source bias voltage (VGS) of the transistor in the conductive state in relation to the one (Vcc) that would be fixed by the output of the logic circuit (11) in the absence of such a bias circuit (41).
Dependencies are inferred from the claim text.