US 2001/0017558 A1 · Semiconductor integrated circuit having a clock recovery circuit

Abstract

A clock recovery circuit is provided for use in a memory with a clock synchronized interface, wherein an external clock is temporarily intercepted to shorten lock-in time when an internal clock is to be generated from the external clock. The clock recovery circuit includes a delay circuit array, receiving the external clock, for generating reference clocks, a control circuit comparing phases of the external clock and of the reference clocks and detecting the number of delay stages required for locking in, and a latching circuit for holding the number of delay stages required for locking in. Once synchronism is detected, the generation of internal clock can be resumed in a short period of time even if the supply of the external clock is temporarily suspended.

Claims6

Dependent claims

A semiconductor integrated circuit having a clock recovery circuit which receives an external clock and generates an internal clock,

wherein said clock recovery circuit comprises:
an input standard node, to which said external clock is coupled, for supplying a first standard clock;
a plurality of first delay circuits, whose initial stage is coupled to said input standard node, for supplying a plurality of reference clocks differing in phase from each other;
and
a control circuit having a comparator for detecting a predetermined number of delay stages required for locking in by comparing the plurality of reference clocks with said first standard clock and detecting the reference clock closest in phase to said first standard clock, and a latch circuit for holding information on said predetermined number of delay stages,
wherein said plurality of first delay circuits supply said internal clock correspondingly to said predetermined number of delay stages detected by said control circuit.

3 more elements

A semiconductor integrated circuit having a clock recovery circuit which receives an external clock and generates an internal clock, wherein said clock recovery circuit comprises:

an input buffer, which receives said external clock, for supplying a standard clock from a first node;
a first delay circuit array having a first input node coupled to said first node;
a plurality of first delay circuits connected in series;
whose input end is coupled to said first input node;
and a plurality of first output nodes, provided in each of the connecting nodes of said plurality of first delay circuits, for supplying a plurality of second clocks;
a control circuit having a second input node coupled to said first node;
a plurality of reference signal input nodes coupled to said plurality of first output nodes;
and a plurality of reference result output nodes;
a second delay circuit array having a third input node coupled to said first node;
a plurality of control signal input nodes coupled to said plurality of reference result output nodes;
a plurality of second delay circuits connected in series, each provided correspondingly to said plurality of control input nodes;
and a second output node coupled to the output of the final stage of said plurality of second delay circuits;
a second node coupled to said second output node;
and
an output buffer circuit, coupled to said second node, for supplying said internal clock, and
wherein said control circuit compares the phases of said first clock entered into said second input node with that of a plurality of clock signals entered into said plurality of reference signal input nodes from said first delay circuit array, detects as the lock-in stage one of said plurality of reference signal nodes into which the closest one of said plurality of clock signals in phase;
and supplies a predetermined signal for the lock-in stage to one of a plurality of comparison result output nodes corresponding to said lock-in stage, and
wherein said second delay circuit array enters said standard clock into one of said plurality of second delay circuits corresponding to said plurality of control signal input nodes into which said predetermined signal for the lock-in stage is entered, causing the clock to propagate through a predetermined number of said second delay circuits, and supplying it to said second output node.

15 more elements

Dependencies are inferred from the claim text.

Semiconductor integrated circuit having a clock recovery circuit

Life of this patent

Semiconductor integrated circuit having a clock recovery circuit

Life of this patent

Abstract

Claims6