Circuit for data signal recovery and clock signal regeneration
AssigneeInfineon Technologies AG
InventorsDirk Friedrich, Michael Rozmann
Life of this patent
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Abstract
The data and clock regeneration circuit can be completely integrated in a chip. The circuit has, in series, two independent PLL regulating stages which are optimally adjustable separately. The first PLL regulating stage has a large bandwidth and is optimized for maximum jitter tolerance and the second PLL regulating stage has a small bandwidth and is optimized for minimum jitter transfer. The circuit is suitable for use, for example, in transceivers for ATM, SONET, and SDH applications with signal transmission links in the Gbit range.
Claims6
A circuit for data signal recovery and clock signal regeneration from an incoming serial data signal stream comprising data bits, comprising:
- a first PLL regulating stage having a voltage-controlled oscillator, an input receiving a serial data signal stream, and an output outputting a clock signal;
- a second PLL regulating stage connected to said output of said first PLL regulating stage and in series therewith, said second PLL regulating stage having an input receiving the clock signal and an output outputting an output clock signal;
- said first and second PLL regulating stages being independent of one another and each being optimally adjustable separately, whereby said first PLL regulating stage is set at a first bandwidth, and said second PLL regulating stage is set at a second bandwidth smaller than the first bandwidth.
Dependencies are inferred from the claim text.