Memory latency compensation
AssigneeAgilent Technologies, Inc.
InventorTHOMAS HENKEL
Life of this patent
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AssigneeAgilent Technologies, Inc.
InventorTHOMAS HENKEL
Estimating the term…
An impact of a memory latency time on repeat operations with a memory is reduced by providing a repeat start buffer for buffering a beginning of a data sequence to be repeatedly accessed, and a repeat switching unit, connected with the memory and the repeat start buffer, for switching therebetween for accessing the buffered beginning of the data sequence to be repeatedly accessed when the data sequence is to be repeated. In case of jump operations, a further reduction is achieved by providing a first and a second data buffer connectable with the memory for buffering data sequences, and a switching unit, connected with the data buffers for switching therebetween. The memory is accessible for each data buffer during an idle memory accessing time of the other data buffer for buffering a beginning of a data sequence to be accessed successively.
An apparatus for accessing a memory means comprising:
An apparatus for accessing a memory means comprising:
A method for repeatedly accessing a memory means for reading and/or writing a data sequence, the method comprising the steps of:
A method for accessing different areas in a memory means comprising the steps of:
Dependencies are inferred from the claim text.