Apparatus for improving alignment for metal masking

A semiconductor wafer polishing method comprising:

• forming at least one alignment mark within an alignment area on a surface of a semiconductor wafer;
• forming a structure about the alignment mark and extending elevationally from the surface from which the alignment mark extends;
• forming a layer to be polished over the structure, the layer being formed to be generally elevationally higher proximately about and surrounding the alignment area than within the alignment area;
• and
• polishing the layer.

A semiconductor wafer polishing method comprising:

• forming at least one alignment mark within an alignment area on a semiconductor wafer;
• forming a series of raised structures in adjacent spaced-apart relation about the alignment mark and extending elevationally from a lowermost portion of the alignment mark;
• forming a layer to be polished over the raised structures, the layer being formed to be generally elevationally higher about the alignment area than within the alignment area;
• and
• polishing the layer.

A semiconductor wafer polishing method comprising:

• preparing a semiconductor substrate having a surface including an alignment marking area;
• depositing a raised portion on the surface to encompass the alignment marking area;
• depositing a removable layer over the wafer including over the raised portion and the alignment marking area;
• providing alignment trenches within the removable layer and within the alignment marking area to form alignment trenches;
• depositing a contrasting layer on the removable layer and within the alignment trenches;
• and
• chemical-mechanical polishing to remove the contrasting layer deposited over the removable layer and expose alignment marks comprising the contrasting layer deposited within the alignment trenches.

A method for improving alignment for metal masking with an oxide and tungsten chemical-mechanical polishing planarization process comprising the following steps:

• preparing a semiconductor substrate having a surface including an alignment marking area;
• depositing a raised portion on the surface to encompass the alignment marking area;
• depositing a removable oxide layer over the wafer including over the raised portion and the alignment marking area;
• forming alignment trenches in a portion of the removable layer within the alignment marking area;
• depositing a contrasting tungsten layer on the removable layer and within the alignment trenches;
• and
• chemical-mechanical polishing to remove the contrasting layer deposited over the removable layer and expose alignment marks comprising the tungsten layer deposited within the alignment trenches of the oxide layer.

A semiconductor wafer, comprising;

• an alignment marking area formed relative to a surface of the wafer;
• at least one alignment mark provided within the alignment area;
• a structure formed about the alignment marking area and extending from the wafer surface a greater elevation than any elevation from such surface from which the alignment mark extends;
• and
• a layer of material to be polished provided over the structure to cause the material to be polished to be elevationally higher over the structure than over the alignment mark.