Semiconductor device and a method of manufacturing the same

A semiconductor device in which an insulated gate field effect transistor and a protection diode connected with a gate for protecting the transistor are constituted to a semiconductor main body comprising a semiconductor substrate of a first protection type and a semiconductor layer of a first conduction type formed on the upper surface of the semiconductor substrate, wherein

• the insulated gate field effect transistor comprises:
• a first region and a second region of a second conduction type opposite to the first conduction type situated being spaced apart from each other on one main surface of a semiconductor layer defined by a device isolation region on both sides of a channel-forming region, the second region comprising a low impurity concentration region in contact with a region to be formed with a channel and a high impurity concentration region in contact with the low concentration region,
• a gate electrode formed above the channel region by way of a gate insulation film,
• a first leach-through layer of a first conduction type formed to a portion of the first main surface so as to be in contact with the first region and the semiconductor substrate,
• a first insulation film covering the gate electrode, the first region, the second region and the first leach-through layer,
• a first conductor plug, a second conductor plug and a third conductor plug connected, respectively, with the first region, the high impurity concentration region of the second region and the first leach-through layer through openings disposed in the first insulation film,
• a first conductor layer connected with the first conductor plug and the third conductor plug, and a second conductor layer connected with the second conductor plug, and
• a third conductor layer connected with the lower surface of the semiconductor substrate, and
• the protection diode is a back-to-back diode comprising:
• a third region of a second conduction type formed to a second main surface of the semiconductor layer defined with a device isolation region, and
• a fourth region and a fifth region of a first conduction type formed in the third region and constituted with the fourth region, the third region and the fifth region.

A semiconductor device comprising:

• a P type silicon substrate,
• a P type silicon semiconductor layer situated to one main surface of the substrate and having an impurity concentration lower than that of the substrate,
• a first N type region and a second N type region disposed being spaced from each other within a main surface of a semiconductor layer,
• a third N type region situated between the first N type region and the second N type region in the main surface of the semiconductor region, being spaced apart from the first N type region and in contact with the second N type region, and having an impurity concentration lower than that of the second N type region,
• a gate electrode disposed by way of a gate insulation film and situated between the first N type region and the third N type region on the main surface of the semiconductor layer to be formed with a channel, overlapping at the ends thereof on the first region and the third region respectively, and terminating on the first region and the third region respectively,
• a first electrode and a second electrode connected with the first region and the second region, respectively and
• a third electrode connected with the other main surface of the semiconductor substrate opposite to one main surface in which
• the distribution of the impurity concentration in the semiconductor layer situated between the first N type region and the third N type region comprises a P type distribution area increasing from the surface of the semiconductor layer to the semiconductor substrate and an N type distribution area overlapping on the P type distribution area and decreasing from the surface of the semiconductor layer to the semiconductor substrate.

A semiconductor device comprising:

• a P type silicon semiconductor substrate,
• a P type silicon semiconductor layer situated on one main surface of the substrate and having an impurity concentration lower than that of the substrate,
• a first N type region and a second N type region disposed being spaced apart from each other in the main surface of the semiconductor layer,
• a third N type region situated between the first N type region and the second N type region in the main surface of the semiconductor layer, being spaced apart from the first N type region and in contact with the second N type region and having an impurity concentration lower than that of the second N type region.
• a gate electrode disposed by way of the gate insulation film and situated between the first N type region and the third N type region on the main surface of the semiconductor layer to be formed with a channel, so as to overlap at the ends thereof on the first region and the third region, respectively, and terminate on the first region and the third region, respectively,
• a first electrode and a second electrode connected, respectively, with the first region and the second region, and
• a third electrode connected with the other main surface of the semiconductor substrate opposite to the one main surface, in which
• the distribution of the impurity concentration in the semiconductor layer situated between the first N type region and the third N type region comprises a P type distribution area increasing from the surface of the semiconductor layer to the semiconductor substrate and an N type distribution area overlapping on the P type distribution area and having a peak for the impurity concentration at the inside spaced apart from the surface of the semiconductor layer.

A semiconductor device comprising:

• a semiconductor substrate of a first conduction type,
• a semiconductor layer of a first conduction type situated to one main surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate,
• a first region and a second region of a second conduction type opposite to the first conduction type disposed being spaced apart from each other in the main surface of the semiconductor layer.
• a third region situated between the first region and the second region in the main surface of the semiconductor layer, being spaced apart from the first region and in contact with the second region and having an impurity concentration lower than that of the first region,
• a gate electrode disposed by way of a gate insulation film on the main surface of the semiconductor layer and situated between the first region and the third region, so as to overlap at a portion thereof with the first region and the third region, respectively,
• a first electrode and a second electrode connected, respectively, with the first region and the second region, and
• a third electrode connected to the other main surface of the semiconductor substrate opposite to one main surface, in which
• a fourth region of a first conduction type terminating in the third region is formed selectively to the main surface of the semiconductor layer situated between the first region and the third region, and having
• a pocket layer of a first conduction type having an impurity concentration higher than the impurity concentration at the surface of the fourth region being disposed in the fourth region situated below the gate electrode at a position deeper than the third region.

A semiconductor device comprising:

• a semiconductor substrate of a first conduction type,
• a semiconductor layer of a first conduction type situated to one main surface of the substrate and having an impurity concentration lower than that of the semiconductor substrate,
• a first region and a second region of a second conduction type opposite to the first conduction type disposed being space apart from each other in the main surface of the semiconductor layer,
• a third region disposed between the first region and the second region in the main surface of the semiconductor layer, situated being spaced apart from the first region and in contact with the second region and having an impurity concentration lower than that of the first region,
• a gate electrode disposed by way of a gate insulation film on the main surface of the semiconductor layer and situated between the first region and the third region, so as to overlap at a portion thereof on the first region and the third region, respectively,
• a first electrode and a second electrode connected, respectively, with the first region and the second region,
• a third electrode connected with the other main surface opposite to one main surface of the semiconductor substrate, in which
• the first film thickness of the gate insulation film present between overlap of the third region and the gate electrode is greater than the second film thickness of the gate insulation film on the main surface of the semiconductor layer situated between the first region and the third region.

A semiconductor device comprising:

• (1) a semiconductor substrate of a first conduction type,
• (2) a semiconductor layer of a first conduction type disposed on one main surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate,
• (3) a first region and a second region of a second conduction type opposite to the first conduction type disposed being spaced from each other in the main surface of the semiconductor layer,
• (4) a third region situated in the main surface of the semiconductor layer between the first region and the second region, being spaced apart from the first region and in contact with the second region, and having an impurity concentration lower than that in the first region.
• (5) a gate electrode disposed by way of a gate insulation film on the main surface of the semiconductor layer and situated between the first region and the third region, so as to overlap at a portion thereof on the first region and the third region, respectively.
• (6) a first electrode and a second electrode connected, respectively, with the first region and the second region, and
• (7) a third electrode connected to the other main surface opposite to one main surface of the semiconductor substrate, in which
• a bird's beak is present between overlap of the third region and the gate electrode and
• the concentration of the impurity on the surface of the third region is substantially equal with or higher than the impurity concentration of the second region.

A semiconductor device comprising;

• a substrate in which a semiconductor layer of a first conduction type having a low impurity concentration is formed at the main surface,
• a first region and a second region of a second conduction type opposite to the first conduction type disposed, being spaced apart from each other, in the main surface of the semiconductor layer,
• a third region disposed in the main surface of the semiconductor layer between the first region and the second region, being spaced apart from the first region and in contact with the second region, and having an impurity concentration lower than that of the first region,
• a gate electrode situated by way of a gate insulation film on the main surface of the semiconductor layer and situated between the first region and the third region so as to overlap at a portion thereof with the first region and the third region, respectively, and
• a well region of a first conduction type formed in the semiconductor layer below the gate insulation film, in which
• the first film thickness of the gate insulation film present between overlap of the third region gate electrode is formed at a thickness greater than the second film thickness of the gate insulation film on the main surface of the semiconductor layer situated between the first region and the third region, and the third region comprises a shallow high concentration region and a deep low concentration region.

A semiconductor device comprising:

• a semiconductor substrate of a first conduction type,
• a semiconductor layer of a first conduction type formed on a main surface of the substrate,
• a first region and a second region of a second conduction type opposite to the first conduction type situated, being spaced apart from each other, in the main surface of the semiconductor layer,
• a third region of a second conduction type formed on the main surface of the conductor layer between the first region and the second region, so as to be spaced apart from the first region and in contact with the second region,
• a gate oxide film disposed to the main surface of the semiconductor layer as a channel region between the first region and the third region,
• a gate conductor layer disposed on the gate oxide film,
• a first conductor layer connected with the first region,
• a second conductor layer connected with the second region, and
• a third conductor layer connected with the rearface of the semiconductor substrate, in which
• the film thickness for each of the first gate oxide film situated between the first region and the gate insulation film and a second gate oxide film situated between the third region and the gate insulation film is greater than the thickness of the third gate oxide film disposed to the main surface of the semiconductor layer as the channel region.

An insulated gate type semiconductor device having, on the main surface of a semiconductor layer, a plurality of channel regions, a drain region and a source region disposed on both side of each of the channel regions, and a conductor layer for a gate electrode disposed by way of a gate insulation film on each of the channel region surfaces, wherein

• a metal plug is connected with the main surface of each of the drain regions and each of the source regions,
• a first metal conductor layer is connected with each of the metal plugs,
• an interlayer insulation film is covered on the first metal conductor layer,
• a second metal conductor layer for the drain is connected in common with each of the first metal conductor layers for the drain of the first metal conductor layers through the openings for the connection of drain disposed to the interlayer insulation film being situated on the metal plug connected with the drain region,
• a second metal conductor layer for the source is connected in common with each of the first metal conductor layers for the source of the first metal conductor layers through the source connecting openings disposed to the interlayer insulation film,
• a second metal conductor layer for the gate is connected in common with each of the first metal conductor layers for the gate of the first metal conductor layers through the gate connecting openings disposed to the interlayer insulation film,
• the second metal conductor layer for the drain has a drain bonding pad, and
• the second metal conductor layer for the gate has a gate bonding pad.

An insulated gate type semiconductor device having a plurality of channel regions, a drain region and a source region disposed on both sides of each of the channel regions and a conductor layer for the gate electrode disposed to the surface of each of the channel regions by way of a gate insulation film to a main surface of a semiconductor chip having a semiconductor layer, and including insulated type field effect transistors as a unit block, wherein

• a metal plug is connected with the main surface of each of the drain regions and each of the source regions,
• a first metal conductor layer is connected with each of metal plugs,
• an interlayer insulation film is covered on the first metal conductor layer,
• a second metal conductor layer for the drain is connected in common with each of the first metal conductor layers for the drain of the first metal conductor layers through drain connecting openings disposed to the interlayer insulation film being situated on the metal plug connected with the drain region,
• a second metal conductor layer for the source is connected in common with each of the first metal conductor layers for the source of the first metal conductor layers through source connecting openings disposed to the interlayer insulation film,
• a second metal conductor layer for the gate is connected in common with each of the first metal conductor layers for the gate of the first metal conductor layers through gate connecting openings disposed to the interlayer insulation film,
• the second metal conductor layer for the drain having a drain bonding pad and
• the second metal conductor layer for the gate has a gate bonding pad, and wherein
• the insulated gate type field effect transistors of the unit block are disposed in plurality to the main surface of the semiconductor chip.

An insulated gate type semiconductor device having a plurality of channel regions, a drain region and a source region disposed on both sides of each of the channel regions, and a conductor layer for the gate electrode disposed by way of a gate insulation film to the surface of each of the channel regions to a main surface of a semiconductor chip having a semiconductor layer, and including insulated gate type field effect transistors as a unit block, wherein

• metal plugs are connected with the main surface of each of the drain regions and each of the source regions,
• a first metal conductor layer is connected with each of the metal plugs,
• an interlayer insulation film is covered on the first metal conductor layer,
• a second metal conductor layer for the drain is connected in common with each of the first metal conductor layers for the drain of the first metal conductor layers through drain connecting openings disposed in the interlayer insulation film being situated on the metal plug connected with the drain region,
• a second metal conductor layer for the source is connected in common with each of the first metal conductor layers for the source of the first metal conductor layers through source connecting openings disposed in the interlayer insulation film,
• a second metal conductor layer for the gate is connected in common with each of the first metal conductor layers for the gate of the first metal conductor layers through gate connecting openings disposed in the interlayer insulation film,
• the second metal conductor layer for the drain has a drain bonding pad,
• the second metal conductor layer for the gate has a gate bonding pad, and wherein
• the insulated gate type field effect transistors of the unit block are disposed in plurality on the main surface of the semiconductor substrate, and
• the first metal conductor layer for the gate and the second metal conductor layer for the gate are connected between each of the unit blocks.

An insulated gate type semiconductor device having a plurality of channel regions, a drain region and a source region disposed on both sides of each of the channel regions, and a conductor layer for the gate electrode disposed by way of a gate insulation film to the surface of each of the channel regions to a main surface of a semiconductor chip having a semiconductor layer, wherein

• metal plugs are connected to the main surface of each of the drain regions and each of the source regions,
• a first metal conductor layer is connected with each of the metal plugs,
• an interlayer insulation film is covered on the first metal conductor layer,
• a second metal conductor layer for the drain is connected in common with each of the first metal conductor layers for the drain of the first metal conductor layers through drain connecting openings disposed in the interlayer insulation film being situated on the metal plugs connected with the drain regions,
• a second metal conductor layer for the gate is connected in common with each of the first metal conductor layers for the gate of the first metal conductor layers through gate connecting openings disposed to the interlayer insulation film,
• the second metal conductor layer for the drain has a drain bonding pad,
• the second metal conductor layer for the gate has a gate bonding pad,
• the drain region is a common drain region put between the channel regions and
• the conductor layers for the gate electrodes are disposed independently of each other.

A method of manufacturing a semiconductor device comprising a semiconductor substrate of a first conduction type, a semiconductor layer of a first conduction type formed to the upper surface of the semiconductor substrate, a field insulation film formed for defining a device forming region to the main surface of the semiconductor layer, a first region and a second region of a second conduction type opposite to the first conduction type situated, being spaced apart from each other, in the device forming region on both sides of a region to be formed with a channel, the second region comprising a low impurity concentration region in contact with a region to be formed with the channel and a high impurity concentration region in contact with the low impurity concentration region, and having a gate electrode formed by way of a gate insulation film above the channel region, and a leach-through layer of a first conduction type formed in the device forming region so as to be in contact with the first region and the semiconductor substrate, wherein the method comprises

• a step of introducing impurities for forming the leach-through layer selectively on the main surface of the semiconductor layer,
• a step of forming the field insulation film selectively to the main surface of the semiconductor layer by thermal oxidation, and extending the impurities to form the leach-through layer in contact with the semiconductor substrate,
• a step of forming the gate insulation film to the surface of the device forming region defined by the field insulation film,
• a step of forming the gate electrode on the gate insulation film and then
• a step of forming the first region and the second region in the device forming region.

A method of manufacturing a semiconductor device comprising:

• (1) a step of preparing a semiconductor substrate having a semiconductor layer of a first conduction type at the main surface,
• (2) a step of introducing impurities of a first conduction type selectively for forming a leach-through layer extending to the semiconductor substrate on the main surface of the semiconductor layer,
• (3) a step of selectively forming a field insulation film for defining a device forming region to the main surface of the semiconductor layer by thermal oxidation,
• (4) a step of forming a gate insulation film to the surface of the device forming region defined by the field insulation film,
• (5) a step of forming a gate electrode on the gate insulation film,
• (6) a step of forming an offset region of the first conduction type in self alignment to the gate electrode in the device forming region,
• (7) a step of forming a first region of a first conduction type self aligned with the gate electrode, and forming a second region of a first conduction type being spaced apart from the gate electrode end and being in contact with the offset region and having an impurity concentration higher than that of the offset region, respectively, and, successively,
• (8) a step of forming a first insulation film so as to cover the device forming region,
• (9) a step of forming openings to the first insulation film for exposing the main surfaces of the first region and the second region and the leach-through layer,
• (10) a step of forming first, second and third metal plugs connected with the main surfaces of the first region and the second region and the leach-through layer, respectively, in the openings,
• (11) a step of forming a first conductor layer of connecting the first metal plug and the third metal plug to each other and forming a second conductor layer for connection with the second metal plug, respectively, by patterning and
• (12) a step of forming a third conductor layer to the rearface of the semiconductor substrate.

A high frequency module constituting an amplifier circuit with a plurality of semiconductor chips constituting insulated gate type field effect transistors, in which each of the semiconductor chips includes an insulated gate type field effect transistor as a unit block, each comprising

• a plurality of channel regions a drain region and a source region disposed on both sides of each of the channel regions, and a conductor layer for a gate electrode on the main surface of a semiconductor substrate having a semiconductor layer disposed by way of a gate insulation film on the surface of each of the channel regions, in which metal plugs are connected to the main surfaces of each of the drain regions and each of the source regions, wherein
• a first metal conductor layer is connected with each of the metal plugs,
• an interlayer insulation film is covered on the first metal conductor layer,
• a second metal conductor layer for the drain is connected in common with each of the first metal conductor layers for the drain of the first metal conductor layers through drain connection openings disposed to the interlayer insulation film being situated on the metal plug connected with the drain region,
• a second conductor layer for the source is connected in common with each of the first metal conductor layers for the source of the first metal conductor layers through source connection openings disposed to the interlayer insulation film,
• a second conductor layer for the gate is connected in common with each of the first metal conductor layers for the gate of the first metal conductor layers through gate connection openings disposed to the interlayer insulation film,
• the second metal conductor layer for the drain has a drain bonding pad, and
• the second metal conductor layer for the gate has a gate bonding pad, and
• the insulated gate type field effect transistors of the unit block are disposed in plurality on the main surface of the semiconductor layer.