Single feature size mos technology power device

A process for manufacturing a MOS technology power device, comprising the steps of:

• forming a first insulating material layer over a semiconductor material of a first conductivity type;
• forming a first conductive material layer over the first insulating material layer;
• forming a second insulating material layer over the first conductive material layer;
• selectively removing the second insulating material layer and the first conductive material layer to open at least one elongated window therein, the elongated window having elongated edges;
• forming a body region of a second conductivity type in the semiconductor material layer under the elongated window;
• forming a source region of the first conductivity type in the body region and a body portion of the body region wherein no dopants of the first conductivity type are provided;
• forming insulating material sidewall spacers above the semiconductor material along the longitudinal edges of the elongated window;
• forming a second conductive material layer over the second insulating material layer, the second conductive material layer contacting the source region and the body region through the elongated window.

MOS-gated apparatus, comprising:

• a semiconductor material of a first conductivity type;
• a plurality of body regions of a second conductivity type formed in a surface of the semiconductor material;
• a source region of the first conductivity type formed in a surface of each body region;
• an insulated gate layer disposed above the surface of the semiconductor material, the insulated gate layer having a plurality of windows in the insulating gate layer, each window in the insulating gate layer exposing a respective source region and a respective body region and having one dimension that is limited only by an optical resolution limit of a photolithographic apparatus used to define the window, the insulated gate layer including:
• a first insulating layer material disposed above the surface of the semiconductor material;
• a conductive layer disposed above the first insulating material layer;
• and
• a second insulating material layer disposed above the conductive layer;
• a plurality of sidewall spacers, each side wall spacer disposed at an edge of the insulated gate layer in a respective window in the insulated gate layer and sealing the edge of the insulated gate layer;
• and
• a metal layer disposed above the insulated gate layer and contacting each of the plurality of body regions and each of the plurality of source regions through the plurality of windows.

A process for forming a MOS-gated apparatus, comprising the steps of:

• providing a semiconductor substrate including a semiconductor material layer of a first conductivity type disposed over a highly doped semiconductor substrate;
• forming an insulated gate layer over a surface of the semiconductor material layer;
• selectively removing the insulated gate layer to provide a plurality of windows in the insulated gate layer exposing the semiconductor material layer beneath each window, wherein each window has a transverse dimension that is limited only by an optical resolution limit of a photolithographic apparatus used to form each window;
• forming a respective body region of a second conductivity type in the surface of the semiconductor material layer through the respective window in the insulated gate layer;
• forming a source region of the first conductivity type in each body region;
• forming a plurality of sidewall spacers, each sidewall space disposed along a lateral edge of each window in the insulated gate layer above the surface of the semiconductor material layer;
• and
• forming a metal layer above the insulated gate layer and above the semiconductor material layer and contacting each body region and each source region through each window in the insulated gate layer.