Timing fuse option for row repair
AssigneeMicron Technology, Inc.
InventorBRIAN M. SHIRLEY
Life of this patent
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Abstract
A fuse option for a dynamic random access memory (DRAM) is provided to selectively slow row address signals when redundant rows of memory cells have been selected for use. The fuse option is blown when a redundant row is used to replace a defective row as identified during manufacture of a DRAM. The fuse is coupled to delay circuitry which has a known delay. When the fuse is blown after detecting a defective row, the delay circuitry is coupled in series with selected portions of a row address strobe (RAS) chain of circuitry used to propagate row address selection signals to the proper rows. This provides extra time needed for row address compare and override circuitry, which is not in series with the delay circuitry.
Claims20
A semiconductor memory device comprising:
- a plurality of rows of memory cells;
- a redundant row of memory cells;
- a row address strobe circuit operable for producing a row address strobe;
- and
- a fuse coupled to the row address strobe circuit operable for controlling the speed of the row address strobe
A dynamic random access memory device comprising:
- a memory array having a plurality of rows of memory cells;
- a plurality of redundant rows of memory cells;
- a control circuit for providing a row address strobe signal;
- and
- a settable option coupled to the control circuit for controlling the speed of the row address stobe.
A dynamic random access memory device comprising:
- a memory array having a plurality of rows of memory cells;
- a plurality of redundant rows of memory cells;
- a row decoder comprising a fuse bank coupled to the memory array and the redundant rows of memory cells;
- a control circuit coupled to the row decoder for providing a row address strobe signal;
- and
- a settable option coupled to the control circuit.
A dynamic random access memory device comprising:
- a memory array having a plurality of rows of memory cells;
- a plurality of redundant rows of memory cells;
- a row decoder comprising a fuse bank coupled to the memory array and the redundant rows of memory cells;
- a control circuit coupled to the row decoder for providing row address strobe signals at a selectable speed;
- and
- a settable option coupled to the control circuit for selecting the speed at which the row address strobe signals are provided.
A method of delaying row address strobe signals in a semiconductor memory device, comprising the steps of:
- enabling a spare row of memory cells;
- and
- setting an option to delay the row address strobe signals.
A method of delaying row address strobe signals in a semiconductor memory device, comprising the steps of:
- enabling a spare row of memory cells;
- and
- setting a fuse in a state to delay the row address strobe signals.
A method of delaying row address strobe signals in a semiconductor memory device, comprising the steps of:
- probe testing the memory device at a wafer level;
- detecting a bad row of memory cells;
- setting a redundancy fuse to enable a spare row of memory cells for use in place of the bad row of memory cells;
- and
- setting a fast/slow fuse in a state to delay the row address strobe signals.
A computer system, the computer system comprising a memory device, the memory device including:
- a plurality of rows of memory cells;
- a redundant row of memory cells;
- a row address strobe circuit operable for producing a row address strobe;
- and
- a fuse coupled to the row address strobe circuit operable for controlling the speed of the row address strobe
Dependencies are inferred from the claim text.