High-voltage device and method for manufacturing high-voltage device

A method for manufacturing a high-voltage device, comprising the steps of:

• providing a P-type substrate and an N-type substrate;
• forming a first P-type well region and a second P-type well region respectively in the P-type substrate and the N-type substrate;
• forming a first N-type well region and a second N-type well region respectively in the P-type substrate and the N-type substrate;
• forming a plurality of first field oxide layers and a plurality of second oxide layers respectively on the first N-type well region and the second P-type well region, wherein each of the first field oxide layers possesses a first N-type doped region beneath the first field oxide layer and each of the second field oxide layers possesses a first P-type doped region beneath the second field oxide layer;
• forming a first and a second shallow trench isolations respectively in the first N-type well region between the first field oxide layers and in the second P-type well region between the second field oxide layers;
• forming a third P-type well region in the first P-type well region while a second P-type doped region is formed in the first N-type well region beneath the first shallow trench isolation;
• forming a third N-type well region in the second N-type well region while a second N-type doped region is formed in the second P-type well region beneath second the shallow trench isolation;
• forming a first and a second gate structures respectively on the P-type substrate between the first P-type and the first N-type regions and on the N-type substrate between the second N-type and the second P-type well regions, wherein the first gate structure laterally expands to cover a portion of the first and the third P-type well regions and the first field oxide layer and the second gate structure laterally expands to cover a portion of the second and the third N-type well regions and the field second oxide layer;
• forming an N-type source and an N-type drain respectively in the third P-type well region and the first N-type well region exposed by the first gate structure and the first field oxide layer;
• and
• forming a P-type source and a P-type drain respectively in the third N-type well region and the second P-type well region exposed by the second gate structure and the second field oxide layer.

A method for forming a high-voltage device, comprising the steps of:

• providing a substrate having a first conductive type;
• forming a first well region with the first conductive type in the substrate;
• forming a second well region with a second conductive type in the substrate;
• forming a pad oxide layer and a patterned silicon nitride layer on the substrate in sequence;
• forming a plurality of first doped regions with the second conductive type respectively in the second well region under portions of the pad oxide layer exposed by the patterned silicon nitride layer;
• forming a plurality of field oxide layers respectively on portions of the pad oxide layer above the first doped regions;
• removing the patterned silicon nitride layer and the pad oxide layer;
• forming a shallow trench isolation in the second well region between the field oxide layers;
• forming a third well region with the first conductive type in the first well region while a second doped region with the first conductive type is formed in the second well region beneath the shallow trench isolation;
• forming a gate structure on the substrate between the first and second well regions, wherein the gate structure laterally expands to cover a portion of the first well region, the third well region, and the field oxide layer;
• and
• forming a source with the second conductive type and a drain with the second conductive type respectively in the third well region and the second well region exposed by the gate structure and the field oxide layer.