Back to results
US 2001/0011744 A1Published application
New poly spacer split gate cell with extremely small cell size
AssigneeMosel Vitelic, Inc.
InventorKuo-Tung Sung
Life of this patent
Estimating the term…
Abstract
A dual-gate cell structure with self-aligned gates. A polysilicon spacer forms a second gate (213) separated from a first gate (201), which is also polysilicon, by a dielectric layer (207). A drain region (219) and a source region (221) are formed next to the gates within a shallower well. The shallower well is positioned above a deep well region. In one embodiment, the second gate (213) acts as a floating gate in a flash cell. The floating gate may be programmed and erased by the application of appropriate voltage levels to the first gate (201), source (221), and/or drain (219). The self-aligned nature of the second gate (213) to the first gate (201) allows a very small dual-gate cell to be formed.
Claims32
A semiconductor device comprising:
- a substrate having a first conductivity type and a substrate doping concentration;
- a first well region disposed within the substrate, the first well region having a second conductivity type;
- a second well region disposed within the substrate, the second well region having the first conductivity type;
- a drain region disposed within the substrate, the drain region having the second conductivity type;
- a source region disposed within the substrate, the source region having the second conductivity type;
- a first dielectric layer disposed between
- a first gate and the substrate, wherein the first gate has a first sidewall;
- a second gate having a second sidewall, the second gate being self-aligned to the first gate by
- a second dielectric layer disposed between the first sidewall and the second sidewall;
- and
- a channel region including a first portion and a second portion disposed in the substrate, said channel region disposed within the second well region and between the drain region and the source region, wherein the first portion of the channel region is separated from a portion of the first gate by the first dielectric layer, and the second portion of the channel region is separated from a portion of the second gate by the second dielectric layer.
8 more elements
A semiconductor device structure comprising:
- a substrate having a first conductivity type and a substrate doping concentration;
- a deep well region disposed within the substrate, the deep well region having a second conductivity type;
- a shallower well region disposed within the substrate, the shallower well region having the first conductivity type;
- a drain region disposed within the shallower well region, the drain region having the second conductivity type;
- a source region disposed within the shallower well region, the source region having the second conductivity type;
- a first dielectric layer comprising silicon oxide disposed between
- a first gate and the substrate, wherein the first gate comprises polycide and has a first sidewall;
- a floating gate comprising polysilicon and having a second sidewall, the second gate being self-aligned to the first gate by
- a second dielectric layer comprising silicon oxy-nitride disposed between the first sidewall and the second sidewall;
- and
- a channel region including a first portion and a second portion disposed in the shallower well region between the drain region and the source region, wherein the first portion of the channel region is separated from a portion of the first gate by the first dielectric layer, and the second portion of the channel region is separated from a portion of the second gate by the second dielectric layer.
8 more elements
A semiconductor device structure comprising:
- a substrate having a first conductivity type and a substrate doping concentration;
- a first well region disposed within the substrate, the first well region having a second conductivity type;
- a second well region disposed within the substrate, the second well region having the first conductivity type;
- a drain region disposed within the substrate, the drain region having the second conductivity type;
- a source region disposed within the substrate, the source region having the second conductivity type;
- a first dielectric layer;
- a first gate separated from the substrate by the first dielectric layer, wherein the first gate has a first sidewall and a distal surface distal from the substrate;
- a second gate having a second sidewall, the second gate being self-aligned to the first gate by a first portion of the first dielectric layer disposed between the first sidewall and the second sidewall;
- and
- a channel region including a first portion and a second portion disposed in the substrate, said channel region disposed within the second well region and between the drain region and the source region, wherein the first portion of the channel region is separated from a portion of the first polysilicon gate by a second portion of the first dielectric layer, and the second portion of the channel region is separated from a portion of the second gate by a second dielectric layer.
7 more elements
A method of forming a non-volatile memory cell comprising steps of:
- (a) providing a semiconductor substrate having a first conductivity type;
- (b) forming a first region in the substrate having a second conductivity type opposite to the first conductivity type;
- (c) forming a second region in the substrate having the first conductivity type;
- (d) forming a first dielectric layer on a surface of the semiconductor substrate;
- (e) forming a first conductive layer on the first dielectric layer;
- (f) patterning the first conductive layer and first dielectric layer to form a first gate structure separated from the semiconductor substrate by the first dielectric layer, and to form an exposed portion of the surface of the semiconductor substrate;
- (g) forming a second dielectric layer on a sidewall of the first gate structure and on the exposed portion of the surface of the semiconductor substrate;
- (h) forming a second conductive layer on the second dielectric layer;
- (i) patterning the second conductive layer to form a first spacer and a second spacer, the first spacer and the second spacer being separated from the first gate structure by the second dielectric layer;
- (j) removing the second spacer;
- and
- (k) forming a third region in the substrate proximate to an opposite sidewall of the first gate structure and a fourth region in the substrate proximate to an edge of the first spacer, the third region and the fourth region disposed within the second region and having the second conductivity type.
9 more elements
A method of forming a non-volatile memory cell comprising steps of:
- (a) providing a semiconductor substrate having a first conductivity type;
- (b) forming a first region in the substrate having a second conductivity type opposite to the first conductivity type;
- (c) forming a second region in the substrate having the first conductivity type;
- (d) forming a first dielectric layer on a surface of the semiconductor substrate;
- (e) defining a trench in the first dielectric layer;
- (f) forming a high-quality dielectric layer to line the trench;
- (g) forming a first conductive layer over the high-quality dielectric layer to substantially fill the trench to form a first gate structure;
- (h) removing at least a portion of the first dielectric layer and a portion of the first conductive layer other than the first gate structure to expose the high-quality dielectric layer on a sidewall of the first gate structure;
- (i) forming a second dielectric layer over the surface of the semiconductor substrate proximate to the sidewall of the first gate structure;
- (j) forming a second conductive layer over at least the second dielectric layer;
- (k) patterning the second conductive layer to form a first spacer separated from the sidewall of the first gate structure by the high-quality dielectric layer and a second spacer on an opposite sidewall of the first gate structure;
- (l) removing the second spacer;
- and
- (m) forming a third region in the substrate proximate to the opposite sidewall of the first gate structure, and a fourth region in the substrate proximate to an edge of the first spacer, the third region and the fourth region disposed in the second region and having the second conductivity type.
11 more elements
Dependencies are inferred from the claim text.